Module Name: src
Committed By: kiyohara
Date: Mon Jul 4 15:45:38 UTC 2016
Modified Files:
src/sys/arch/arm/omap: omap3_sdhc.c omap3_sdmmcreg.h
src/sys/arch/evbarm/conf: BEAGLEBONE
Log Message:
AM335x's sdhc@obio use offset 0x100.
Oops this space maybe use HL registers? OMAP4430 use this space.
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/omap/omap3_sdhc.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/omap/omap3_sdmmcreg.h
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/evbarm/conf/BEAGLEBONE
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/omap/omap3_sdhc.c
diff -u src/sys/arch/arm/omap/omap3_sdhc.c:1.20 src/sys/arch/arm/omap/omap3_sdhc.c:1.21
--- src/sys/arch/arm/omap/omap3_sdhc.c:1.20 Mon Apr 25 13:20:42 2016
+++ src/sys/arch/arm/omap/omap3_sdhc.c Mon Jul 4 15:45:37 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: omap3_sdhc.c,v 1.20 2016/04/25 13:20:42 kiyohara Exp $ */
+/* $NetBSD: omap3_sdhc.c,v 1.21 2016/07/04 15:45:37 kiyohara Exp $ */
/*-
* Copyright (c) 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap3_sdhc.c,v 1.20 2016/04/25 13:20:42 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap3_sdhc.c,v 1.21 2016/07/04 15:45:37 kiyohara Exp $");
#include "opt_omap.h"
#include "edma.h"
@@ -243,8 +243,13 @@ obiosdhc_attach(device_t parent, device_
clksft = ffs(sc->sc.sc_clkmsk) - 1;
+#if defined(TI_AM335X)
+ error = bus_space_map(sc->sc_bst, oa->obio_addr + OMAP4_SDMMC_HL_SIZE,
+ oa->obio_size - OMAP4_SDMMC_HL_SIZE, 0, &sc->sc_bsh);
+#else
error = bus_space_map(sc->sc_bst, oa->obio_addr, oa->obio_size, 0,
&sc->sc_bsh);
+#endif
if (error) {
aprint_error_dev(self,
"can't map registers: %d\n", error);
@@ -261,7 +266,7 @@ obiosdhc_attach(device_t parent, device_
cv_init(&sc->sc_edma_cv, "sdhcedma");
sc->sc_edma_fifo = oa->obio_addr +
- OMAP3_SDMMC_SDHC_OFFSET + SDHC_DATA;
+ OMAP4_SDMMC_HL_SIZE + OMAP3_SDMMC_SDHC_OFFSET + SDHC_DATA;
sc->sc.sc_flags |= SDHC_FLAG_USE_DMA;
sc->sc.sc_flags |= SDHC_FLAG_EXTERNAL_DMA;
sc->sc.sc_flags |= SDHC_FLAG_EXTDMA_DMAEN;
Index: src/sys/arch/arm/omap/omap3_sdmmcreg.h
diff -u src/sys/arch/arm/omap/omap3_sdmmcreg.h:1.7 src/sys/arch/arm/omap/omap3_sdmmcreg.h:1.8
--- src/sys/arch/arm/omap/omap3_sdmmcreg.h:1.7 Sat Jul 27 17:10:28 2013
+++ src/sys/arch/arm/omap/omap3_sdmmcreg.h Mon Jul 4 15:45:37 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: omap3_sdmmcreg.h,v 1.7 2013/07/27 17:10:28 jklos Exp $ */
+/* $NetBSD: omap3_sdmmcreg.h,v 1.8 2016/07/04 15:45:37 kiyohara Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -45,13 +45,15 @@
#define SDMMC4_BASE_4430 0x480D1000 // same for omap5
#define SDMMC5_BASE_4430 0x480D5000 // same for omap5
-#define SDMMC1_BASE_TIAM335X 0x48060100
-#define SDMMC2_BASE_TIAM335X 0x481d8100
-#define SDMMC3_BASE_TIAM335X 0x47810100
+#define SDMMC1_BASE_TIAM335X 0x48060000
+#define SDMMC2_BASE_TIAM335X 0x481d8000
+#define SDMMC3_BASE_TIAM335X 0x47810000
#define OMAP3_SDMMC_SDHC_OFFSET 0x100
#define OMAP3_SDMMC_SDHC_SIZE 0x100
+#define OMAP4_SDMMC_HL_SIZE 0x100
+
#define MMCHS_SYSCONFIG 0x010 /* System Configuration */
# define SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
# define SYSCONFIG_CLOCKACTIVITY_FCLK (2 << 8)
Index: src/sys/arch/evbarm/conf/BEAGLEBONE
diff -u src/sys/arch/evbarm/conf/BEAGLEBONE:1.35 src/sys/arch/evbarm/conf/BEAGLEBONE:1.36
--- src/sys/arch/evbarm/conf/BEAGLEBONE:1.35 Mon Jul 4 15:35:55 2016
+++ src/sys/arch/evbarm/conf/BEAGLEBONE Mon Jul 4 15:45:38 2016
@@ -1,5 +1,5 @@
#
-# $NetBSD: BEAGLEBONE,v 1.35 2016/07/04 15:35:55 kiyohara Exp $
+# $NetBSD: BEAGLEBONE,v 1.36 2016/07/04 15:45:38 kiyohara Exp $
#
# BEAGLEBONE -- TI AM335x board Kernel
#
@@ -196,16 +196,13 @@ prcm0 at obio0 addr 0x44e00000 size 0x2
sitaracm0 at obio0 addr 0x44e10000 size 0x2000
# SDHC controllers
-# XXX Kludge -- the am335x's mmc registers start at an offset of #x100
-# from other omap3. (What about omap4?) Need to adapt the omap sdhc
-# driver to handle this.
-sdhc0 at obio1 addr 0x48060100 size 0x0f00 intr 64 edmabase 24
+sdhc0 at obio1 addr 0x48060000 size 0x1000 intr 64 edmabase 24
sdmmc0 at sdhc0
ld0 at sdmmc0
-sdhc1 at obio1 addr 0x481d8100 size 0x0f00 intr 28 edmabase 2 # BB Black
+sdhc1 at obio1 addr 0x481d8000 size 0x1000 intr 28 edmabase 2 # BB Black
sdmmc1 at sdhc1
ld1 at sdmmc1
-#sdhc2 at obio0 addr 0x47810100 size 0xff00 intr 29
+#sdhc2 at obio0 addr 0x47810000 size 0x1000 intr 29
#sdmmc2 at sdhc2
#ld2 at sdmmc2
sdmmc* at sdhc? # SD/MMC bus
