Module Name: src
Committed By: dholland
Date: Mon Jul 4 15:52:31 UTC 2016
Modified Files:
src/sys/arch/mips/mips: locore_mips1.S mipsX_subr.S
Log Message:
More of previous, so both kern_intr and user_intr have the comment.
To generate a diff of this commit:
cvs rdiff -u -r1.86 -r1.87 src/sys/arch/mips/mips/locore_mips1.S
cvs rdiff -u -r1.66 -r1.67 src/sys/arch/mips/mips/mipsX_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/locore_mips1.S
diff -u src/sys/arch/mips/mips/locore_mips1.S:1.86 src/sys/arch/mips/mips/locore_mips1.S:1.87
--- src/sys/arch/mips/mips/locore_mips1.S:1.86 Mon Jul 4 15:47:04 2016
+++ src/sys/arch/mips/mips/locore_mips1.S Mon Jul 4 15:52:31 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_mips1.S,v 1.86 2016/07/04 15:47:04 dholland Exp $ */
+/* $NetBSD: locore_mips1.S,v 1.87 2016/07/04 15:52:31 dholland Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -495,7 +495,11 @@ NESTED_NOPROFILE(MIPSX(kern_intr), KERNF
INT_S t1, CPU_INFO_IDEPTH(s2) # store new interrupt depth
/*
- * Now we can enable interrupts since no interrupts can be delivered
+ * Now that we're at splhigh so all interrupts are masked
+ * individually and we won't get interrupted here, turn the
+ * global interrupt enable bit on again. This will allow
+ * high-priority interrupts to be delivered once a
+ * low-priority interrupt handler lowers spl to execute.
*/
mfc0 v1, MIPS_COP_0_STATUS
nop
Index: src/sys/arch/mips/mips/mipsX_subr.S
diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.66 src/sys/arch/mips/mips/mipsX_subr.S:1.67
--- src/sys/arch/mips/mips/mipsX_subr.S:1.66 Mon Jul 4 15:47:04 2016
+++ src/sys/arch/mips/mips/mipsX_subr.S Mon Jul 4 15:52:31 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.66 2016/07/04 15:47:04 dholland Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.67 2016/07/04 15:52:31 dholland Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -1457,8 +1457,13 @@ NESTED_NOPROFILE(MIPSX(user_intr), CALLF
move s0, v0 # remember previous priority
/*
- * Now we can turn off the FPU, clear exception level, and enter
- * kernel mode since no interrupts can be delivered
+ * Now that we're at splhigh so all interrupts are masked
+ * individually and we won't get interrupted here, clear the
+ * exception level bit. This will allow high-priority
+ * interrupts to be delivered once a low-priority interrupt
+ * handler lowers spl to execute.
+ *
+ * Also turn off the FPU and enter kernel mode.
*/
mfc0 v1, MIPS_COP_0_STATUS
#ifdef NOFPU
