Module Name: src
Committed By: dholland
Date: Mon Jul 4 15:47:04 UTC 2016
Modified Files:
src/sys/arch/mips/mips: locore_mips1.S mipsX_subr.S
Log Message:
Improve comments after some discussion with Nick.
To generate a diff of this commit:
cvs rdiff -u -r1.85 -r1.86 src/sys/arch/mips/mips/locore_mips1.S
cvs rdiff -u -r1.65 -r1.66 src/sys/arch/mips/mips/mipsX_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/locore_mips1.S
diff -u src/sys/arch/mips/mips/locore_mips1.S:1.85 src/sys/arch/mips/mips/locore_mips1.S:1.86
--- src/sys/arch/mips/mips/locore_mips1.S:1.85 Thu Jun 11 07:30:10 2015
+++ src/sys/arch/mips/mips/locore_mips1.S Mon Jul 4 15:47:04 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_mips1.S,v 1.85 2015/06/11 07:30:10 matt Exp $ */
+/* $NetBSD: locore_mips1.S,v 1.86 2016/07/04 15:47:04 dholland Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -771,8 +771,13 @@ NESTED_NOPROFILE(MIPSX(user_intr), CALLF
move s0, v0 # remember previous priority
/*
- * Now that we are at IPL_HIGH, we can turn off FPU and turn on
- * interrupts since they all masked.
+ * Now that we're at splhigh so all interrupts are masked
+ * individually and we won't get interrupted here, turn the
+ * global interrupt enable bit on again. This will allow
+ * high-priority interrupts to be delivered once a
+ * low-priority interrupt handler lowers spl to execute.
+ *
+ * Also switch off the FPU.
*/
mfc0 v1, MIPS_COP_0_STATUS
#ifndef NOFPU
Index: src/sys/arch/mips/mips/mipsX_subr.S
diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.65 src/sys/arch/mips/mips/mipsX_subr.S:1.66
--- src/sys/arch/mips/mips/mipsX_subr.S:1.65 Mon Jul 4 14:47:39 2016
+++ src/sys/arch/mips/mips/mipsX_subr.S Mon Jul 4 15:47:04 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.65 2016/07/04 14:47:39 dholland Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.66 2016/07/04 15:47:04 dholland Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -1083,7 +1083,11 @@ NESTED_NOPROFILE(MIPSX(kern_intr), KERNF
INT_S t1, CPU_INFO_IDEPTH(s2) # store new interrupt depth
/*
- * Now we can clear exception level since no interrupts can be delivered
+ * Now that we're at splhigh so all interrupts are masked
+ * individually and we won't get interrupted here, clear the
+ * exception level bit. This will allow high-priority
+ * interrupts to be delivered once a low-priority interrupt
+ * handler lowers spl to execute.
*/
mfc0 v1, MIPS_COP_0_STATUS
MFC0_HAZARD
