CVS commit: src/sys/arch/mips/mips

[Michael Lorenz]

Module Name:    src
Committed By:   macallan
Date:           Wed Jul 13 21:25:15 UTC 2016

Modified Files:
        src/sys/arch/mips/mips: cache_r10k.c

Log Message:
make this compile again


To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/mips/mips/cache_r10k.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/arch/mips/mips/cache_r10k.c
diff -u src/sys/arch/mips/mips/cache_r10k.c:1.7 src/sys/arch/mips/mips/cache_r10k.c:1.8
--- src/sys/arch/mips/mips/cache_r10k.c:1.7	Mon Jul 11 16:15:36 2016
+++ src/sys/arch/mips/mips/cache_r10k.c	Wed Jul 13 21:25:15 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: cache_r10k.c,v 1.7 2016/07/11 16:15:36 matt Exp $	*/
+/*	$NetBSD: cache_r10k.c,v 1.8 2016/07/13 21:25:15 macallan Exp $	*/
 
 /*-
  * Copyright (c) 2003 Takao Shinohara.
@@ -91,9 +91,10 @@ r10k_icache_sync_all(void)
 	__asm volatile("sync");
 
 	while (va < eva) {
-		cache_op_r4k_line(va+0, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
-		cache_op_r4k_line(va+1, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
-		va += 64;
+		cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
+		va++;
+		cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
+		va += 63;
 	}
 }
 
@@ -141,9 +142,10 @@ r10k_icache_sync_range_index(vaddr_t va,
 	va = trunc_line(va);
 
 	while (va < eva) {
-		cache_op_r4k_line(va+0, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
-		cache_op_r4k_line(va+1, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
-		va += 64;
+		cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
+		va++;
+		cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
+		va += 63;
 	}
 }
 
@@ -161,9 +163,10 @@ r10k_pdcache_wbinv_all(void)
 	vaddr_t eva = va + mci->mci_pdcache_way_size;
 
 	while (va < eva) {
-		cache_op_r4k_line(va+0, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
-		cache_op_r4k_line(va+1, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
-		va += 32;
+		cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+		va++;
+		cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+		va += 31;
 	}
 }
 
@@ -198,9 +201,10 @@ r10k_pdcache_wbinv_range_index(vaddr_t v
 	va = trunc_line(va);
 
 	while (va < eva) {
-		cache_op_r4k_line(va+0, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
-		cache_op_r4k_line(va+1, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
-		va += 32;
+		cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+		va++;
+		cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+		va += 31;
 	}
 }
 
@@ -246,9 +250,10 @@ r10k_sdcache_wbinv_all(void)
 	vsize_t line_size = mci->mci_sdcache_line_size;
 
 	while (va < eva) {
-		cache_op_r4k_line(va+0, CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
-		cache_op_r4k_line(va+1, CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
-		va += line_size;
+		cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
+		va++;
+		cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
+		va += line_size - 1;
 	}
 }
 
@@ -286,9 +291,10 @@ r10k_sdcache_wbinv_range_index(vaddr_t v
 	va = trunc_line(va);
 
 	while (va < eva) {
-		cache_op_r4k_line(va+0, CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
-		cache_op_r4k_line(va+1, CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
-		va += line_size;
+		cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
+		va++;
+		cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
+		va += line_size - 1;
 	}
 }