Module Name: src
Committed By: skrll
Date: Tue Jul 26 05:52:55 UTC 2016
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Set the cause register to zero after disabling interrupts now that spl0
doesn't do it.
My cobalt now boots (again again)
To generate a diff of this commit:
cvs rdiff -u -r1.202 -r1.203 src/sys/arch/mips/mips/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/locore.S
diff -u src/sys/arch/mips/mips/locore.S:1.202 src/sys/arch/mips/mips/locore.S:1.203
--- src/sys/arch/mips/mips/locore.S:1.202 Mon Jul 11 16:15:36 2016
+++ src/sys/arch/mips/mips/locore.S Tue Jul 26 05:52:55 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.202 2016/07/11 16:15:36 matt Exp $ */
+/* $NetBSD: locore.S,v 1.203 2016/07/26 05:52:55 skrll Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -97,6 +97,8 @@ _C_LABEL(kernel_text):
mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts
COP0_SYNC
#endif
+ mtc0 zero, MIPS_COP_0_CAUSE
+ COP0_SYNC
#ifdef MIPS64_OCTEON
//
// U-boot on the erlite starts all cpus at the kernel entry point.
