Module Name: src
Committed By: skrll
Date: Mon Aug 15 14:44:44 UTC 2016
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Typo in comment
To generate a diff of this commit:
cvs rdiff -u -r1.88 -r1.89 src/sys/arch/mips/mips/mipsX_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/mipsX_subr.S
diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.88 src/sys/arch/mips/mips/mipsX_subr.S:1.89
--- src/sys/arch/mips/mips/mipsX_subr.S:1.88 Mon Aug 15 14:26:48 2016
+++ src/sys/arch/mips/mips/mipsX_subr.S Mon Aug 15 14:44:44 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.88 2016/08/15 14:26:48 skrll Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.89 2016/08/15 14:44:44 skrll Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -360,7 +360,7 @@
*
* Loongson2 processors don't have separate tlbmiss and xtlbmiss handlers;
* so we have to check for useg addresses in tlb_miss. The good news is that
- * we can use 64 intructions form tlbmiss instead of 32.
+ * we can use 64 intructions from tlbmiss instead of 32.
*
*----------------------------------------------------------------------------
*/
