Module Name: src
Committed By: ryo
Date: Wed Oct 5 15:39:31 UTC 2016
Modified Files:
src/sys/arch/mips/ralink: ralink_eth.c ralink_reg.h
Log Message:
KNF; indent, spaces and tabs.
No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/mips/ralink/ralink_eth.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/mips/ralink/ralink_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ralink/ralink_eth.c
diff -u src/sys/arch/mips/ralink/ralink_eth.c:1.9 src/sys/arch/mips/ralink/ralink_eth.c:1.10
--- src/sys/arch/mips/ralink/ralink_eth.c:1.9 Fri Jun 10 13:27:12 2016
+++ src/sys/arch/mips/ralink/ralink_eth.c Wed Oct 5 15:39:31 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: ralink_eth.c,v 1.9 2016/06/10 13:27:12 ozaki-r Exp $ */
+/* $NetBSD: ralink_eth.c,v 1.10 2016/10/05 15:39:31 ryo Exp $ */
/*-
* Copyright (c) 2011 CradlePoint Technology, Inc.
* All rights reserved.
@@ -29,7 +29,7 @@
/* ralink_eth.c -- Ralink Ethernet Driver */
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ralink_eth.c,v 1.9 2016/06/10 13:27:12 ozaki-r Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ralink_eth.c,v 1.10 2016/10/05 15:39:31 ryo Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -63,12 +63,12 @@ __KERNEL_RCSID(0, "$NetBSD: ralink_eth.c
#include <mips/ralink/ralink_reg.h>
#if 0
#define CPDEBUG /* XXX TMP DEBUG FIXME */
-#define RALINK_ETH_DEBUG /* XXX TMP DEBUG FIXME */
+#define RALINK_ETH_DEBUG /* XXX TMP DEBUG FIXME */
#define ENABLE_RALINK_DEBUG_ERROR 1
#define ENABLE_RALINK_DEBUG_MISC 1
#define ENABLE_RALINK_DEBUG_INFO 1
#define ENABLE_RALINK_DEBUG_FORCE 1
-#define ENABLE_RALINK_DEBUG_REG 1
+#define ENABLE_RALINK_DEBUG_REG 1
#endif
#include <mips/ralink/ralink_debug.h>
@@ -77,49 +77,49 @@ __KERNEL_RCSID(0, "$NetBSD: ralink_eth.c
struct ralink_rx_desc {
uint32_t data_ptr;
uint32_t rxd_info1;
-#define RXD_LEN1(x) (((x) >> 0) & 0x3fff)
-#define RXD_LAST1 (1 << 14)
-#define RXD_LEN0(x) (((x) >> 16) & 0x3fff)
-#define RXD_LAST0 (1 << 30)
-#define RXD_DDONE (1 << 31)
+#define RXD_LEN1(x) (((x) >> 0) & 0x3fff)
+#define RXD_LAST1 (1 << 14)
+#define RXD_LEN0(x) (((x) >> 16) & 0x3fff)
+#define RXD_LAST0 (1 << 30)
+#define RXD_DDONE (1 << 31)
uint32_t unused;
uint32_t rxd_info2;
-#define RXD_FOE(x) (((x) >> 0) & 0x3fff)
-#define RXD_FVLD (1 << 14)
-#define RXD_INFO(x) (((x) >> 16) & 0xff)
-#define RXD_PORT(x) (((x) >> 24) & 0x7)
-#define RXD_INFO_CPU (1 << 27)
-#define RXD_L4_FAIL (1 << 28)
-#define RXD_IP_FAIL (1 << 29)
-#define RXD_L4_VLD (1 << 30)
-#define RXD_IP_VLD (1 << 31)
+#define RXD_FOE(x) (((x) >> 0) & 0x3fff)
+#define RXD_FVLD (1 << 14)
+#define RXD_INFO(x) (((x) >> 16) & 0xff)
+#define RXD_PORT(x) (((x) >> 24) & 0x7)
+#define RXD_INFO_CPU (1 << 27)
+#define RXD_L4_FAIL (1 << 28)
+#define RXD_IP_FAIL (1 << 29)
+#define RXD_L4_VLD (1 << 30)
+#define RXD_IP_VLD (1 << 31)
};
/* PDMA RX Descriptor Format */
struct ralink_tx_desc {
uint32_t data_ptr0;
uint32_t txd_info1;
-#define TXD_LEN1(x) (((x) & 0x3fff) << 0)
-#define TXD_LAST1 (1 << 14)
-#define TXD_BURST (1 << 15)
-#define TXD_LEN0(x) (((x) & 0x3fff) << 16)
-#define TXD_LAST0 (1 << 30)
-#define TXD_DDONE (1 << 31)
+#define TXD_LEN1(x) (((x) & 0x3fff) << 0)
+#define TXD_LAST1 (1 << 14)
+#define TXD_BURST (1 << 15)
+#define TXD_LEN0(x) (((x) & 0x3fff) << 16)
+#define TXD_LAST0 (1 << 30)
+#define TXD_DDONE (1 << 31)
uint32_t data_ptr1;
uint32_t txd_info2;
-#define TXD_VIDX(x) (((x) & 0xf) << 0)
-#define TXD_VPRI(x) (((x) & 0x7) << 4)
-#define TXD_VEN (1 << 7)
-#define TXD_SIDX(x) (((x) & 0xf) << 8)
-#define TXD_SEN(x) (1 << 13)
-#define TXD_QN(x) (((x) & 0x7) << 16)
-#define TXD_PN(x) (((x) & 0x7) << 24)
-#define TXD_PN_CPU 0
-#define TXD_PN_GDMA1 1
-#define TXD_PN_GDMA2 2
-#define TXD_TCP_EN (1 << 29)
-#define TXD_UDP_EN (1 << 30)
-#define TXD_IP_EN (1 << 31)
+#define TXD_VIDX(x) (((x) & 0xf) << 0)
+#define TXD_VPRI(x) (((x) & 0x7) << 4)
+#define TXD_VEN (1 << 7)
+#define TXD_SIDX(x) (((x) & 0xf) << 8)
+#define TXD_SEN(x) (1 << 13)
+#define TXD_QN(x) (((x) & 0x7) << 16)
+#define TXD_PN(x) (((x) & 0x7) << 24)
+#define TXD_PN_CPU 0
+#define TXD_PN_GDMA1 1
+#define TXD_PN_GDMA2 2
+#define TXD_TCP_EN (1 << 29)
+#define TXD_UDP_EN (1 << 30)
+#define TXD_IP_EN (1 << 31)
};
/* TODO:
@@ -255,7 +255,8 @@ static int ralink_eth_mii_read(device_t
static void ralink_eth_mii_write(device_t, int, int, int);
CFATTACH_DECL_NEW(reth, sizeof(struct ralink_eth_softc),
- ralink_eth_match, ralink_eth_attach, ralink_eth_detach, ralink_eth_activate);
+ ralink_eth_match, ralink_eth_attach, ralink_eth_detach,
+ ralink_eth_activate);
static inline uint32_t
sy_read(const ralink_eth_softc_t *sc, const bus_size_t off)
@@ -317,44 +318,44 @@ ralink_eth_attach(device_t parent, devic
aprint_normal(": Ralink Ethernet\n");
evcnt_attach_dynamic(&sc->sc_evcnt_spurious_intr, EVCNT_TYPE_INTR, NULL,
- device_xname(self), "spurious intr");
+ device_xname(self), "spurious intr");
evcnt_attach_dynamic(&sc->sc_evcnt_rxintr, EVCNT_TYPE_INTR, NULL,
- device_xname(self), "rxintr");
+ device_xname(self), "rxintr");
evcnt_attach_dynamic(&sc->sc_evcnt_rxintr_skip_len,
- EVCNT_TYPE_INTR, &sc->sc_evcnt_rxintr,
- device_xname(self), "rxintr skip: no room for VLAN header");
+ EVCNT_TYPE_INTR, &sc->sc_evcnt_rxintr,
+ device_xname(self), "rxintr skip: no room for VLAN header");
evcnt_attach_dynamic(&sc->sc_evcnt_rxintr_skip_tag_none,
- EVCNT_TYPE_INTR, &sc->sc_evcnt_rxintr,
- device_xname(self), "rxintr skip: no VLAN tag");
+ EVCNT_TYPE_INTR, &sc->sc_evcnt_rxintr,
+ device_xname(self), "rxintr skip: no VLAN tag");
evcnt_attach_dynamic(&sc->sc_evcnt_rxintr_skip_tag_inval,
- EVCNT_TYPE_INTR, &sc->sc_evcnt_rxintr,
- device_xname(self), "rxintr skip: invalid VLAN tag");
+ EVCNT_TYPE_INTR, &sc->sc_evcnt_rxintr,
+ device_xname(self), "rxintr skip: invalid VLAN tag");
evcnt_attach_dynamic(&sc->sc_evcnt_rxintr_skip_inact,
- EVCNT_TYPE_INTR, &sc->sc_evcnt_rxintr,
- device_xname(self), "rxintr skip: partition inactive");
+ EVCNT_TYPE_INTR, &sc->sc_evcnt_rxintr,
+ device_xname(self), "rxintr skip: partition inactive");
evcnt_attach_dynamic(&sc->sc_evcnt_txintr, EVCNT_TYPE_INTR, NULL,
- device_xname(self), "txintr");
+ device_xname(self), "txintr");
evcnt_attach_dynamic(&sc->sc_evcnt_input, EVCNT_TYPE_INTR, NULL,
- device_xname(self), "input");
+ device_xname(self), "input");
evcnt_attach_dynamic(&sc->sc_evcnt_output, EVCNT_TYPE_INTR, NULL,
- device_xname(self), "output");
+ device_xname(self), "output");
evcnt_attach_dynamic(&sc->sc_evcnt_watchdog, EVCNT_TYPE_INTR, NULL,
- device_xname(self), "watchdog");
+ device_xname(self), "watchdog");
evcnt_attach_dynamic(&sc->sc_evcnt_wd_tx,
- EVCNT_TYPE_INTR, &sc->sc_evcnt_watchdog,
- device_xname(self), "watchdog TX timeout");
+ EVCNT_TYPE_INTR, &sc->sc_evcnt_watchdog,
+ device_xname(self), "watchdog TX timeout");
evcnt_attach_dynamic(&sc->sc_evcnt_wd_spurious,
- EVCNT_TYPE_INTR, &sc->sc_evcnt_watchdog,
- device_xname(self), "watchdog spurious");
+ EVCNT_TYPE_INTR, &sc->sc_evcnt_watchdog,
+ device_xname(self), "watchdog spurious");
evcnt_attach_dynamic(&sc->sc_evcnt_wd_reactivate,
- EVCNT_TYPE_INTR, &sc->sc_evcnt_watchdog,
- device_xname(self), "watchdog reactivate");
+ EVCNT_TYPE_INTR, &sc->sc_evcnt_watchdog,
+ device_xname(self), "watchdog reactivate");
evcnt_attach_dynamic(&sc->sc_evcnt_add_rxbuf_hdr_fail,
- EVCNT_TYPE_INTR, NULL,
- device_xname(self), "add rxbuf hdr fail");
+ EVCNT_TYPE_INTR, NULL,
+ device_xname(self), "add rxbuf hdr fail");
evcnt_attach_dynamic(&sc->sc_evcnt_add_rxbuf_mcl_fail,
- EVCNT_TYPE_INTR, NULL,
- device_xname(self), "add rxbuf mcl fail");
+ EVCNT_TYPE_INTR, NULL,
+ device_xname(self), "add rxbuf mcl fail");
/*
* In order to obtain unique initial Ethernet address on a host,
@@ -379,19 +380,19 @@ ralink_eth_attach(device_t parent, devic
if ((error = bus_space_map(sc->sc_memt, RA_SYSCTL_BASE,
sc->sc_sy_size, 0, &sc->sc_sy_memh)) != 0) {
aprint_error_dev(self, "unable to map Sysctl registers, "
- "error=%d\n", error);
+ "error=%d\n", error);
goto fail_0a;
}
if ((error = bus_space_map(sc->sc_memt, RA_FRAME_ENGINE_BASE,
sc->sc_fe_size, 0, &sc->sc_fe_memh)) != 0) {
aprint_error_dev(self, "unable to map Frame Engine registers, "
- "error=%d\n", error);
+ "error=%d\n", error);
goto fail_0b;
}
if ((error = bus_space_map(sc->sc_memt, RA_ETH_SW_BASE,
sc->sc_sw_size, 0, &sc->sc_sw_memh)) != 0) {
aprint_error_dev(self, "unable to map Ether Switch registers, "
- "error=%d\n", error);
+ "error=%d\n", error);
goto fail_0c;
}
@@ -399,29 +400,29 @@ ralink_eth_attach(device_t parent, devic
if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct ralink_descs),
PAGE_SIZE, 0, &sc->sc_dseg, 1, &sc->sc_ndseg, 0)) != 0) {
aprint_error_dev(self, "unable to allocate transmit descs, "
- "error=%d\n", error);
+ "error=%d\n", error);
goto fail_1;
}
if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_ndseg,
- sizeof(struct ralink_descs), (void **)&sc->sc_descs, BUS_DMA_COHERENT))
- != 0) {
+ sizeof(struct ralink_descs), (void **)&sc->sc_descs,
+ BUS_DMA_COHERENT)) != 0) {
aprint_error_dev(self, "unable to map control data, "
- "error=%d\n", error);
+ "error=%d\n", error);
goto fail_2;
}
- if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct ralink_descs), 1,
- sizeof(struct ralink_descs), 0, 0, &sc->sc_pdmamap)) != 0) {
+ if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct ralink_descs),
+ 1, sizeof(struct ralink_descs), 0, 0, &sc->sc_pdmamap)) != 0) {
aprint_error_dev(self, "unable to create control data DMA map, "
- "error=%d\n", error);
+ "error=%d\n", error);
goto fail_3;
}
if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_pdmamap, sc->sc_descs,
sizeof(struct ralink_descs), NULL, 0)) != 0) {
aprint_error_dev(self, "unable to load control data DMA map, "
- "error=%d\n", error);
+ "error=%d\n", error);
goto fail_4;
}
@@ -430,8 +431,9 @@ ralink_eth_attach(device_t parent, devic
if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
RALINK_ETH_MAX_TX_SEGS, MCLBYTES, 0, 0,
&sc->sc_txstate[i].txs_dmamap)) != 0) {
- aprint_error_dev(self, "unable to create tx DMA map %d, "
- "error=%d\n", i, error);
+ aprint_error_dev(self,
+ "unable to create tx DMA map %d, error=%d\n",
+ i, error);
goto fail_5;
}
}
@@ -440,8 +442,9 @@ ralink_eth_attach(device_t parent, devic
for (i = 0; i < RALINK_ETH_NUM_RX_DESC; i++) {
if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
MCLBYTES, 0, 0, &sc->sc_rxstate[i].rxs_dmamap)) != 0) {
- aprint_error_dev(self, "unable to create rx DMA map %d, "
- "error=%d\n", i, error);
+ aprint_error_dev(self,
+ "unable to create rx DMA map %d, error=%d\n",
+ i, error);
goto fail_6;
}
sc->sc_rxstate[i].rxs_mbuf = NULL;
@@ -452,10 +455,10 @@ ralink_eth_attach(device_t parent, devic
/* setup some address in hardware */
fe_write(sc, RA_FE_GDMA1_MAC_LSB,
- (enaddr[5] | (enaddr[4] << 8) |
- (enaddr[3] << 16) | (enaddr[2] << 24)));
+ (enaddr[5] | (enaddr[4] << 8) |
+ (enaddr[3] << 16) | (enaddr[2] << 24)));
fe_write(sc, RA_FE_GDMA1_MAC_MSB,
- (enaddr[1] | (enaddr[0] << 8)));
+ (enaddr[1] | (enaddr[0] << 8)));
/*
* iterate through ports
@@ -476,23 +479,23 @@ ralink_eth_attach(device_t parent, devic
sc->sc_mii.mii_statchg = ralink_eth_mii_statchg;
sc->sc_ethercom.ec_mii = &sc->sc_mii;
ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange,
- ether_mediastatus);
+ ether_mediastatus);
mii_attach(sc->sc_dev, &sc->sc_mii, ~0, i, MII_OFFSET_ANY,
- MIIF_FORCEANEG|MIIF_DOPAUSE|MIIF_NOISOLATE);
+ MIIF_FORCEANEG|MIIF_DOPAUSE|MIIF_NOISOLATE);
if (LIST_EMPTY(&sc->sc_mii.mii_phys)) {
#if 1
ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|
- IFM_FDX|IFM_ETH_RXPAUSE|IFM_ETH_TXPAUSE, 0, NULL);
+ IFM_FDX|IFM_ETH_RXPAUSE|IFM_ETH_TXPAUSE, 0, NULL);
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|
- IFM_FDX|IFM_ETH_RXPAUSE|IFM_ETH_TXPAUSE);
+ IFM_FDX|IFM_ETH_RXPAUSE|IFM_ETH_TXPAUSE);
#else
ifmedia_add(&sc->sc_mii.mii_media,
- IFM_ETHER|IFM_MANUAL, 0, NULL);
+ IFM_ETHER|IFM_MANUAL, 0, NULL);
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL);
#endif
} else {
- /* Ensure we mask ok for the switch multiple phy's */
+ /* Ensure we mask ok for the switch multiple phy's */
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
}
@@ -510,9 +513,9 @@ ralink_eth_attach(device_t parent, devic
/* We support IPV4 CRC Offload */
ifp->if_capabilities |=
- (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
- IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
- IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx);
+ (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
+ IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
+ IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx);
/* Attach the interface. */
if_attach(ifp);
@@ -532,20 +535,20 @@ ralink_eth_attach(device_t parent, devic
for (i = 0; i < RALINK_ETH_NUM_RX_DESC; i++) {
if (sc->sc_rxstate[i].rxs_dmamap != NULL)
bus_dmamap_destroy(sc->sc_dmat,
- sc->sc_rxstate[i].rxs_dmamap);
+ sc->sc_rxstate[i].rxs_dmamap);
}
fail_5:
for (i = 0; i < RALINK_ETH_NUM_TX_DESC; i++) {
if (sc->sc_txstate[i].txs_dmamap != NULL)
bus_dmamap_destroy(sc->sc_dmat,
- sc->sc_txstate[i].txs_dmamap);
+ sc->sc_txstate[i].txs_dmamap);
}
bus_dmamap_unload(sc->sc_dmat, sc->sc_pdmamap);
fail_4:
bus_dmamap_destroy(sc->sc_dmat, sc->sc_pdmamap);
fail_3:
bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs,
- sizeof(struct ralink_descs));
+ sizeof(struct ralink_descs));
fail_2:
bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_ndseg);
fail_1:
@@ -600,12 +603,12 @@ ralink_eth_enable(ralink_eth_softc_t *sc
int s = splnet();
ralink_eth_hw_init(sc);
sc->sc_ih = ra_intr_establish(RA_IRQ_FENGINE,
- ralink_eth_intr, sc, 1);
+ ralink_eth_intr, sc, 1);
splx(s);
if (sc->sc_ih == NULL) {
RALINK_DEBUG(RALINK_DEBUG_ERROR,
- "%s: unable to establish interrupt\n",
- device_xname(sc->sc_dev));
+ "%s: unable to establish interrupt\n",
+ device_xname(sc->sc_dev));
return EIO;
}
@@ -675,7 +678,7 @@ ralink_eth_detach(device_t self, int fla
bus_dmamap_unload(sc->sc_dmat, sc->sc_pdmamap);
bus_dmamap_destroy(sc->sc_dmat, sc->sc_pdmamap);
bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs,
- sizeof(struct ralink_descs));
+ sizeof(struct ralink_descs));
bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_ndseg);
bus_space_unmap(sc->sc_memt, sc->sc_sw_memh, sc->sc_sw_size);
@@ -732,41 +735,41 @@ ralink_eth_hw_init(ralink_eth_softc_t *s
#if defined(RT3050) || defined(RT3052)
/* Bring the switch to a sane default state (from linux driver) */
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_SGC2,
- 0x00000000);
+ 0x00000000);
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PFC1,
- 0x00405555); /* check VLAN tag on port forward */
+ 0x00405555); /* check VLAN tag on port forward */
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_VLANI0,
- 0x00002001);
+ 0x00002001);
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PVIDC0,
- 0x00001002);
+ 0x00001002);
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PVIDC1,
- 0x00001001);
+ 0x00001001);
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PVIDC2,
- 0x00001001);
+ 0x00001001);
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_VMSC0,
- 0xffff417e);
+ 0xffff417e);
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_POC0,
- 0x00007f7f);
+ 0x00007f7f);
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_POC2,
- 0x00007f3f);
+ 0x00007f3f);
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_FTC2,
- 0x00d6500c);
+ 0x00d6500c);
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_SWGC,
- 0x0008a301); /* hashing algorithm=XOR48 */
+ 0x0008a301); /* hashing algorithm=XOR48 */
/* aging interval=300sec */
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_SOCPC,
- 0x02404040);
+ 0x02404040);
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_FPORT,
- 0x3f502b28); /* Change polling Ext PHY Addr=0x0 */
+ 0x3f502b28); /* Change polling Ext PHY Addr=0x0 */
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_FPA,
- 0x00000000);
+ 0x00000000);
/* do some mii magic TODO: define these registers/bits */
/* lower down PHY 10Mbps mode power */
/* select local register */
ralink_eth_mii_write(sc->sc_dev, 0, 31, 0x8000);
- for (i=0;i<5;i++){
+ for (i=0; i < 5; i++) {
/* set TX10 waveform coefficient */
ralink_eth_mii_write(sc->sc_dev, i, 26, 0x1601);
@@ -799,14 +802,14 @@ ralink_eth_hw_init(ralink_eth_softc_t *s
#else
/* GE1 + GigSW */
fe_write(sc, RA_FE_MDIO_CFG1,
- MDIO_CFG_PHY_ADDR(0x1f) |
- MDIO_CFG_BP_EN |
- MDIO_CFG_FORCE_CFG |
- MDIO_CFG_SPEED(MDIO_CFG_SPEED_1000M) |
- MDIO_CFG_FULL_DUPLEX |
- MDIO_CFG_FC_TX |
- MDIO_CFG_FC_RX |
- MDIO_CFG_TX_CLK_MODE(MDIO_CFG_TX_CLK_MODE_3COM));
+ MDIO_CFG_PHY_ADDR(0x1f) |
+ MDIO_CFG_BP_EN |
+ MDIO_CFG_FORCE_CFG |
+ MDIO_CFG_SPEED(MDIO_CFG_SPEED_1000M) |
+ MDIO_CFG_FULL_DUPLEX |
+ MDIO_CFG_FC_TX |
+ MDIO_CFG_FC_RX |
+ MDIO_CFG_TX_CLK_MODE(MDIO_CFG_TX_CLK_MODE_3COM));
#endif
/*
@@ -841,8 +844,8 @@ ralink_eth_hw_init(ralink_eth_softc_t *s
* to avoid the flush?
*/
bus_dmamap_sync(sc->sc_dmat, sc->sc_pdmamap,
- (int)&sc->sc_txdesc - (int)sc->sc_descs, sizeof(sc->sc_txdesc),
- BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+ (int)&sc->sc_txdesc - (int)sc->sc_descs, sizeof(sc->sc_txdesc),
+ BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
/* Initialize the RX descriptor ring */
memset(sc->sc_rxdesc, 0, sizeof(sc->sc_rxdesc));
@@ -858,8 +861,8 @@ ralink_eth_hw_init(ralink_eth_softc_t *s
* to avoid the flush?
*/
bus_dmamap_sync(sc->sc_dmat, sc->sc_pdmamap,
- (int)&sc->sc_rxdesc - (int)sc->sc_descs, sizeof(sc->sc_rxdesc),
- BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+ (int)&sc->sc_rxdesc - (int)sc->sc_descs, sizeof(sc->sc_rxdesc),
+ BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
/* Clear the PDMA state */
r = fe_read(sc, RA_FE_PDMA_GLOBAL_CFG);
@@ -879,36 +882,36 @@ ralink_eth_hw_init(ralink_eth_softc_t *s
/* Give the TX and TX rings to the chip. */
fe_write(sc, RA_FE_PDMA_TX0_PTR,
- htole32(MIPS_KSEG0_TO_PHYS(&sc->sc_txdesc)));
+ htole32(MIPS_KSEG0_TO_PHYS(&sc->sc_txdesc)));
fe_write(sc, RA_FE_PDMA_TX0_COUNT, htole32(RALINK_ETH_NUM_TX_DESC));
fe_write(sc, RA_FE_PDMA_TX0_CPU_IDX, 0);
fe_write(sc, RA_FE_PDMA_RESET_IDX, PDMA_RST_TX0);
fe_write(sc, RA_FE_PDMA_RX0_PTR,
- htole32(MIPS_KSEG0_TO_PHYS(&sc->sc_rxdesc)));
+ htole32(MIPS_KSEG0_TO_PHYS(&sc->sc_rxdesc)));
fe_write(sc, RA_FE_PDMA_RX0_COUNT, htole32(RALINK_ETH_NUM_RX_DESC));
fe_write(sc, RA_FE_PDMA_RX0_CPU_IDX,
- htole32(RALINK_ETH_NUM_RX_DESC - 1));
+ htole32(RALINK_ETH_NUM_RX_DESC - 1));
fe_write(sc, RA_FE_PDMA_RESET_IDX, PDMA_RST_RX0);
fe_write(sc, RA_FE_PDMA_RX0_CPU_IDX,
- htole32(RALINK_ETH_NUM_RX_DESC - 1));
+ htole32(RALINK_ETH_NUM_RX_DESC - 1));
/* Start PDMA */
fe_write(sc, RA_FE_PDMA_GLOBAL_CFG,
- FE_PDMA_GLOBAL_CFG_TX_WB_DDONE |
- FE_PDMA_GLOBAL_CFG_RX_DMA_EN |
- FE_PDMA_GLOBAL_CFG_TX_DMA_EN |
- FE_PDMA_GLOBAL_CFG_BURST_SZ_4);
+ FE_PDMA_GLOBAL_CFG_TX_WB_DDONE |
+ FE_PDMA_GLOBAL_CFG_RX_DMA_EN |
+ FE_PDMA_GLOBAL_CFG_TX_DMA_EN |
+ FE_PDMA_GLOBAL_CFG_BURST_SZ_4);
/* Setup the clock for the Frame Engine */
fe_write(sc, RA_FE_GLOBAL_CFG,
- FE_GLOBAL_CFG_EXT_VLAN(0x8100) |
- FE_GLOBAL_CFG_US_CLK(RA_BUS_FREQ / 1000000) |
- FE_GLOBAL_CFG_L2_SPACE(0x8));
+ FE_GLOBAL_CFG_EXT_VLAN(0x8100) |
+ FE_GLOBAL_CFG_US_CLK(RA_BUS_FREQ / 1000000) |
+ FE_GLOBAL_CFG_L2_SPACE(0x8));
/* Turn on all interrupts */
fe_write(sc, RA_FE_INT_ENABLE,
- FE_INT_RX | FE_INT_TX3 | FE_INT_TX2 | FE_INT_TX1 | FE_INT_TX0);
+ FE_INT_RX | FE_INT_TX3 | FE_INT_TX2 | FE_INT_TX1 | FE_INT_TX0);
/*
* Configure GDMA forwarding
@@ -917,32 +920,32 @@ ralink_eth_hw_init(ralink_eth_softc_t *s
*/
#if 0
fe_write(sc, RA_FE_GDMA1_FWD_CFG,
- (FE_GDMA_FWD_CFG_DIS_TX_CRC | FE_GDMA_FWD_CFG_DIS_TX_PAD));
+ (FE_GDMA_FWD_CFG_DIS_TX_CRC | FE_GDMA_FWD_CFG_DIS_TX_PAD));
#endif
fe_write(sc, RA_FE_GDMA1_FWD_CFG,
- FE_GDMA_FWD_CFG_JUMBO_LEN(MCLBYTES/1024) |
- FE_GDMA_FWD_CFG_STRIP_RX_CRC |
- FE_GDMA_FWD_CFG_IP4_CRC_EN |
- FE_GDMA_FWD_CFG_TCP_CRC_EN |
- FE_GDMA_FWD_CFG_UDP_CRC_EN);
+ FE_GDMA_FWD_CFG_JUMBO_LEN(MCLBYTES/1024) |
+ FE_GDMA_FWD_CFG_STRIP_RX_CRC |
+ FE_GDMA_FWD_CFG_IP4_CRC_EN |
+ FE_GDMA_FWD_CFG_TCP_CRC_EN |
+ FE_GDMA_FWD_CFG_UDP_CRC_EN);
/* CDMA also needs CRCs turned on */
r = fe_read(sc, RA_FE_CDMA_CSG_CFG);
r |= (FE_CDMA_CSG_CFG_IP4_CRC_EN | FE_CDMA_CSG_CFG_UDP_CRC_EN |
- FE_CDMA_CSG_CFG_TCP_CRC_EN);
+ FE_CDMA_CSG_CFG_TCP_CRC_EN);
fe_write(sc, RA_FE_CDMA_CSG_CFG, r);
/* Configure Flow Control Thresholds */
#ifdef RT3883
fe_write(sc, RA_FE_PSE_FQ_CFG,
- FE_PSE_FQ_MAX_COUNT(0xff) |
- FE_PSE_FQ_FC_RELEASE(0x90) |
- FE_PSE_FQ_FC_ASSERT(0x80));
+ FE_PSE_FQ_MAX_COUNT(0xff) |
+ FE_PSE_FQ_FC_RELEASE(0x90) |
+ FE_PSE_FQ_FC_ASSERT(0x80));
#else
fe_write(sc, RA_FE_PSE_FQ_CFG,
- FE_PSE_FQ_MAX_COUNT(0x80) |
- FE_PSE_FQ_FC_RELEASE(0x50) |
- FE_PSE_FQ_FC_ASSERT(0x40));
+ FE_PSE_FQ_MAX_COUNT(0x80) |
+ FE_PSE_FQ_FC_RELEASE(0x50) |
+ FE_PSE_FQ_FC_ASSERT(0x40));
#endif
#ifdef RALINK_ETH_DEBUG
@@ -950,23 +953,23 @@ ralink_eth_hw_init(ralink_eth_softc_t *s
printf("FE_MDIO_CFG2: 0x%08x\n", fe_read(sc, RA_FE_MDIO_CFG2));
printf("FE_PDMA_TX0_PTR: %08x\n", fe_read(sc, RA_FE_PDMA_TX0_PTR));
printf("FE_PDMA_TX0_COUNT: %08x\n",
- fe_read(sc, RA_FE_PDMA_TX0_COUNT));
+ fe_read(sc, RA_FE_PDMA_TX0_COUNT));
printf("FE_PDMA_TX0_CPU_IDX: %08x\n",
- fe_read(sc, RA_FE_PDMA_TX0_CPU_IDX));
+ fe_read(sc, RA_FE_PDMA_TX0_CPU_IDX));
printf("FE_PDMA_TX0_DMA_IDX: %08x\n",
- fe_read(sc, RA_FE_PDMA_TX0_DMA_IDX));
+ fe_read(sc, RA_FE_PDMA_TX0_DMA_IDX));
printf("FE_PDMA_RX0_PTR: %08x\n", fe_read(sc, RA_FE_PDMA_RX0_PTR));
printf("FE_PDMA_RX0_COUNT: %08x\n",
- fe_read(sc, RA_FE_PDMA_RX0_COUNT));
+ fe_read(sc, RA_FE_PDMA_RX0_COUNT));
printf("FE_PDMA_RX0_CPU_IDX: %08x\n",
- fe_read(sc, RA_FE_PDMA_RX0_CPU_IDX));
+ fe_read(sc, RA_FE_PDMA_RX0_CPU_IDX));
printf("FE_PDMA_RX0_DMA_IDX: %08x\n",
- fe_read(sc, RA_FE_PDMA_RX0_DMA_IDX));
+ fe_read(sc, RA_FE_PDMA_RX0_DMA_IDX));
printf("FE_PDMA_GLOBAL_CFG: %08x\n",
- fe_read(sc, RA_FE_PDMA_GLOBAL_CFG));
+ fe_read(sc, RA_FE_PDMA_GLOBAL_CFG));
printf("FE_GLOBAL_CFG: %08x\n", fe_read(sc, RA_FE_GLOBAL_CFG));
printf("FE_GDMA1_FWD_CFG: %08x\n",
- fe_read(sc, RA_FE_GDMA1_FWD_CFG));
+ fe_read(sc, RA_FE_GDMA1_FWD_CFG));
printf("FE_CDMA_CSG_CFG: %08x\n", fe_read(sc, RA_FE_CDMA_CSG_CFG));
printf("FE_PSE_FQ_CFG: %08x\n", fe_read(sc, RA_FE_PSE_FQ_CFG));
#endif
@@ -1065,16 +1068,16 @@ ralink_eth_add_rxbuf(ralink_eth_softc_t
m->m_ext.ext_size, NULL, BUS_DMA_READ|BUS_DMA_NOWAIT);
if (error) {
aprint_error_dev(sc->sc_dev, "can't load rx DMA map %d, "
- "error=%d\n", idx, error);
+ "error=%d\n", idx, error);
panic(__func__); /* XXX */
}
sc->sc_rxdesc[idx].data_ptr = MIPS_KSEG0_TO_PHYS(
- rxs->rxs_dmamap->dm_segs[0].ds_addr + RALINK_ETHER_ALIGN);
+ rxs->rxs_dmamap->dm_segs[0].ds_addr + RALINK_ETHER_ALIGN);
sc->sc_rxdesc[idx].rxd_info1 = RXD_LAST0;
bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
- rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
+ rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
return 0;
}
@@ -1118,7 +1121,7 @@ ralink_eth_start(struct ifnet *ifp)
if (m0->m_pkthdr.len < RALINK_MIN_BUF) {
int padlen = 64 - m0->m_pkthdr.len;
m_copyback(m0, m0->m_pkthdr.len, padlen,
- sc->ralink_zero_buf);
+ sc->ralink_zero_buf);
/* TODO : need some checking here */
}
@@ -1133,7 +1136,7 @@ ralink_eth_start(struct ifnet *ifp)
MGETHDR(m, M_DONTWAIT, MT_DATA);
if (m == NULL) {
aprint_error_dev(sc->sc_dev,
- "unable to allocate aligned Tx mbuf\n");
+ "unable to allocate aligned Tx mbuf\n");
break;
}
MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner);
@@ -1141,7 +1144,7 @@ ralink_eth_start(struct ifnet *ifp)
MCLGET(m, M_DONTWAIT);
if ((m->m_flags & M_EXT) == 0) {
aprint_error_dev(sc->sc_dev,
- "unable to allocate Tx cluster\n");
+ "unable to allocate Tx cluster\n");
m_freem(m);
break;
}
@@ -1152,8 +1155,8 @@ ralink_eth_start(struct ifnet *ifp)
BUS_DMA_WRITE|BUS_DMA_NOWAIT);
if (error) {
aprint_error_dev(sc->sc_dev,
- "unable to load Tx buffer error=%d\n",
- error);
+ "unable to load Tx buffer error=%d\n",
+ error);
m_freem(m);
break;
}
@@ -1168,38 +1171,38 @@ ralink_eth_start(struct ifnet *ifp)
/* Sync the DMA map. */
bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
- BUS_DMASYNC_PREWRITE);
+ BUS_DMASYNC_PREWRITE);
/* Initialize the transmit descriptor */
sc->sc_txdesc[tx_cpu_idx].data_ptr0 =
- MIPS_KSEG0_TO_PHYS(dmamap->dm_segs[0].ds_addr);
+ MIPS_KSEG0_TO_PHYS(dmamap->dm_segs[0].ds_addr);
sc->sc_txdesc[tx_cpu_idx].txd_info1 =
- TXD_LEN0(dmamap->dm_segs[0].ds_len) | TXD_LAST0;
+ TXD_LEN0(dmamap->dm_segs[0].ds_len) | TXD_LAST0;
sc->sc_txdesc[tx_cpu_idx].txd_info2 =
- TXD_QN(3) | TXD_PN(TXD_PN_GDMA1);
+ TXD_QN(3) | TXD_PN(TXD_PN_GDMA1);
sc->sc_txdesc[tx_cpu_idx].txd_info2 = TXD_QN(3) |
- TXD_PN(TXD_PN_GDMA1) | TXD_VEN |
- // TXD_VIDX(pt->vlan_id) |
- TXD_TCP_EN | TXD_UDP_EN | TXD_IP_EN;
+ TXD_PN(TXD_PN_GDMA1) | TXD_VEN |
+ // TXD_VIDX(pt->vlan_id) |
+ TXD_TCP_EN | TXD_UDP_EN | TXD_IP_EN;
RALINK_DEBUG(RALINK_DEBUG_REG,"+tx(%d) 0x%08x: 0x%08x\n",
- tx_cpu_idx, (int)&sc->sc_txdesc[tx_cpu_idx].data_ptr0,
- sc->sc_txdesc[tx_cpu_idx].data_ptr0);
+ tx_cpu_idx, (int)&sc->sc_txdesc[tx_cpu_idx].data_ptr0,
+ sc->sc_txdesc[tx_cpu_idx].data_ptr0);
RALINK_DEBUG(RALINK_DEBUG_REG,"+tx(%d) 0x%08x: 0x%08x\n",
- tx_cpu_idx, (int)&sc->sc_txdesc[tx_cpu_idx].txd_info1,
- sc->sc_txdesc[tx_cpu_idx].txd_info1);
+ tx_cpu_idx, (int)&sc->sc_txdesc[tx_cpu_idx].txd_info1,
+ sc->sc_txdesc[tx_cpu_idx].txd_info1);
RALINK_DEBUG(RALINK_DEBUG_REG,"+tx(%d) 0x%08x: 0x%08x\n",
- tx_cpu_idx, (int)&sc->sc_txdesc[tx_cpu_idx].data_ptr1,
- sc->sc_txdesc[tx_cpu_idx].data_ptr1);
- RALINK_DEBUG(RALINK_DEBUG_REG,"+tx(%d) 0x%08x: 0x%08x\n", tx_cpu_idx,
- (int)&sc->sc_txdesc[tx_cpu_idx].txd_info2,
- sc->sc_txdesc[tx_cpu_idx].txd_info2);
+ tx_cpu_idx, (int)&sc->sc_txdesc[tx_cpu_idx].data_ptr1,
+ sc->sc_txdesc[tx_cpu_idx].data_ptr1);
+ RALINK_DEBUG(RALINK_DEBUG_REG,"+tx(%d) 0x%08x: 0x%08x\n",
+ tx_cpu_idx, (int)&sc->sc_txdesc[tx_cpu_idx].txd_info2,
+ sc->sc_txdesc[tx_cpu_idx].txd_info2);
/* sync the descriptor we're using. */
bus_dmamap_sync(sc->sc_dmat, sc->sc_pdmamap,
- (int)&sc->sc_txdesc[tx_cpu_idx] - (int)sc->sc_descs,
- sizeof(struct ralink_tx_desc),
- BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+ (int)&sc->sc_txdesc[tx_cpu_idx] - (int)sc->sc_descs,
+ sizeof(struct ralink_tx_desc),
+ BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
/*
* Store a pointer to the packet so we can free it later,
@@ -1210,7 +1213,7 @@ ralink_eth_start(struct ifnet *ifp)
sc->sc_pending_tx++;
if (txs->txs_idx != tx_cpu_idx) {
panic("txs_idx doesn't match %d != %d\n",
- txs->txs_idx, tx_cpu_idx);
+ txs->txs_idx, tx_cpu_idx);
}
SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
@@ -1253,12 +1256,12 @@ ralink_eth_watchdog(struct ifnet *ifp)
if (doing_transmit) {
RALINK_DEBUG(RALINK_DEBUG_ERROR, "%s: transmit timeout\n",
- ifp->if_xname);
+ ifp->if_xname);
ifp->if_oerrors++;
sc->sc_evcnt_wd_tx.ev_count++;
} else {
- RALINK_DEBUG(RALINK_DEBUG_ERROR, "%s: spurious watchog timeout\n",
- ifp->if_xname);
+ RALINK_DEBUG(RALINK_DEBUG_ERROR,
+ "%s: spurious watchog timeout\n", ifp->if_xname);
sc->sc_evcnt_wd_spurious.ev_count++;
return;
}
@@ -1343,11 +1346,11 @@ ralink_eth_intr(void *arg)
RALINK_DEBUG_FUNC_ENTRY();
ralink_eth_softc_t * const sc = arg;
- for (u_int n=0;; n = 1) {
+ for (u_int n = 0;; n = 1) {
u_int32_t status = fe_read(sc, RA_FE_INT_STATUS);
fe_write(sc, RA_FE_INT_STATUS, ~0);
RALINK_DEBUG(RALINK_DEBUG_REG,"%s() status: 0x%08x\n",
- __func__, status);
+ __func__, status);
if ((status & (FE_INT_RX | FE_INT_TX0)) == 0) {
if (n == 0)
@@ -1391,22 +1394,22 @@ ralink_eth_rxintr(ralink_eth_softc_t *sc
rxs = &sc->sc_rxstate[rx_cpu_idx];
bus_dmamap_sync(sc->sc_dmat, sc->sc_pdmamap,
- (int)&sc->sc_rxdesc[rx_cpu_idx] - (int)sc->sc_descs,
- sizeof(struct ralink_rx_desc),
- BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
+ (int)&sc->sc_rxdesc[rx_cpu_idx] - (int)sc->sc_descs,
+ sizeof(struct ralink_rx_desc),
+ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
RALINK_DEBUG(RALINK_DEBUG_REG,"rx(%d) 0x%08x: 0x%08x\n",
- rx_cpu_idx, (int)&sc->sc_rxdesc[rx_cpu_idx].data_ptr,
- sc->sc_rxdesc[rx_cpu_idx].data_ptr);
+ rx_cpu_idx, (int)&sc->sc_rxdesc[rx_cpu_idx].data_ptr,
+ sc->sc_rxdesc[rx_cpu_idx].data_ptr);
RALINK_DEBUG(RALINK_DEBUG_REG,"rx(%d) 0x%08x: 0x%08x\n",
- rx_cpu_idx, (int)&sc->sc_rxdesc[rx_cpu_idx].rxd_info1,
- sc->sc_rxdesc[rx_cpu_idx].rxd_info1);
- RALINK_DEBUG(RALINK_DEBUG_REG,"rx(%d) 0x%08x: 0x%08x\n", rx_cpu_idx,
- (int)&sc->sc_rxdesc[rx_cpu_idx].unused,
- sc->sc_rxdesc[rx_cpu_idx].unused);
+ rx_cpu_idx, (int)&sc->sc_rxdesc[rx_cpu_idx].rxd_info1,
+ sc->sc_rxdesc[rx_cpu_idx].rxd_info1);
RALINK_DEBUG(RALINK_DEBUG_REG,"rx(%d) 0x%08x: 0x%08x\n",
- rx_cpu_idx, (int)&sc->sc_rxdesc[rx_cpu_idx].rxd_info2,
- sc->sc_rxdesc[rx_cpu_idx].rxd_info2);
+ rx_cpu_idx, (int)&sc->sc_rxdesc[rx_cpu_idx].unused,
+ sc->sc_rxdesc[rx_cpu_idx].unused);
+ RALINK_DEBUG(RALINK_DEBUG_REG,"rx(%d) 0x%08x: 0x%08x\n",
+ rx_cpu_idx, (int)&sc->sc_rxdesc[rx_cpu_idx].rxd_info2,
+ sc->sc_rxdesc[rx_cpu_idx].rxd_info2);
if (!(sc->sc_rxdesc[rx_cpu_idx].rxd_info1 & RXD_DDONE))
break;
@@ -1421,7 +1424,7 @@ ralink_eth_rxintr(ralink_eth_softc_t *sc
len = RXD_LEN0(sc->sc_rxdesc[rx_cpu_idx].rxd_info1);
RALINK_DEBUG(RALINK_DEBUG_REG,"rx(%d) packet rx %d bytes\n",
- rx_cpu_idx, len);
+ rx_cpu_idx, len);
/*
* Allocate a new mbuf cluster. If that fails, we are
@@ -1439,7 +1442,7 @@ ralink_eth_rxintr(ralink_eth_softc_t *sc
struct ether_header *eh = mtod(m, struct ether_header *);
printf("rx: eth_dst: %s ", ether_sprintf(eh->ether_dhost));
printf("rx: eth_src: %s type: 0x%04x \n",
- ether_sprintf(eh->ether_shost), ntohs(eh->ether_type));
+ ether_sprintf(eh->ether_shost), ntohs(eh->ether_type));
printf("0x14: %08x\n", *(volatile unsigned int *)(0xb0110014));
printf("0x98: %08x\n", *(volatile unsigned int *)(0xb0110098));
@@ -1465,14 +1468,14 @@ ralink_eth_rxintr(ralink_eth_softc_t *sc
struct ether_header *eh = mtod(m, struct ether_header *);
printf("rx: eth_dst: %s ", ether_sprintf(eh->ether_dhost));
printf("rx: eth_src: %s type: 0x%04x\n",
- ether_sprintf(eh->ether_shost), ntohs(eh->ether_type));
+ ether_sprintf(eh->ether_shost), ntohs(eh->ether_type));
printf("0x14: %08x\n", *(volatile unsigned int *)(0xb0110014));
printf("0x98: %08x\n", *(volatile unsigned int *)(0xb0110098));
unsigned char * s = mtod(m, unsigned char *);
for (int j = 0; j < 32; j++)
printf("%02x%c", *(s + j),
- (j == 15 || j == 31) ? '\n' : ' ');
+ (j == 15 || j == 31) ? '\n' : ' ');
}
#endif
@@ -1514,33 +1517,34 @@ ralink_eth_txintr(ralink_eth_softc_t *sc
*/
while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
bus_dmamap_sync(sc->sc_dmat, sc->sc_pdmamap,
- (int)&sc->sc_txdesc[txs->txs_idx] - (int)sc->sc_descs,
- sizeof(struct ralink_tx_desc),
- BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
-
- RALINK_DEBUG(RALINK_DEBUG_REG,"-tx(%d) 0x%08x: 0x%08x\n", txs->txs_idx,
- (int)&sc->sc_txdesc[txs->txs_idx].data_ptr0,
- sc->sc_txdesc[txs->txs_idx].data_ptr0);
- RALINK_DEBUG(RALINK_DEBUG_REG,"-tx(%d) 0x%08x: 0x%08x\n", txs->txs_idx,
- (int)&sc->sc_txdesc[txs->txs_idx].txd_info1,
- sc->sc_txdesc[txs->txs_idx].txd_info1);
- RALINK_DEBUG(RALINK_DEBUG_REG,"-tx(%d) 0x%08x: 0x%08x\n", txs->txs_idx,
- (int)&sc->sc_txdesc[txs->txs_idx].data_ptr1,
- sc->sc_txdesc[txs->txs_idx].data_ptr1);
- RALINK_DEBUG(RALINK_DEBUG_REG,"-tx(%d) 0x%08x: 0x%08x\n", txs->txs_idx,
- (int)&sc->sc_txdesc[txs->txs_idx].txd_info2,
- sc->sc_txdesc[txs->txs_idx].txd_info2);
+ (int)&sc->sc_txdesc[txs->txs_idx] - (int)sc->sc_descs,
+ sizeof(struct ralink_tx_desc),
+ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
+
+ RALINK_DEBUG(RALINK_DEBUG_REG,"-tx(%d) 0x%08x: 0x%08x\n",
+ txs->txs_idx, (int)&sc->sc_txdesc[txs->txs_idx].data_ptr0,
+ sc->sc_txdesc[txs->txs_idx].data_ptr0);
+ RALINK_DEBUG(RALINK_DEBUG_REG,"-tx(%d) 0x%08x: 0x%08x\n",
+ txs->txs_idx, (int)&sc->sc_txdesc[txs->txs_idx].txd_info1,
+ sc->sc_txdesc[txs->txs_idx].txd_info1);
+ RALINK_DEBUG(RALINK_DEBUG_REG,"-tx(%d) 0x%08x: 0x%08x\n",
+ txs->txs_idx, (int)&sc->sc_txdesc[txs->txs_idx].data_ptr1,
+ sc->sc_txdesc[txs->txs_idx].data_ptr1);
+ RALINK_DEBUG(RALINK_DEBUG_REG,"-tx(%d) 0x%08x: 0x%08x\n",
+ txs->txs_idx, (int)&sc->sc_txdesc[txs->txs_idx].txd_info2,
+ sc->sc_txdesc[txs->txs_idx].txd_info2);
/* we're finished if the current tx isn't done */
if (!(sc->sc_txdesc[txs->txs_idx].txd_info1 & TXD_DDONE))
break;
- RALINK_DEBUG(RALINK_DEBUG_REG,"-tx(%d) transmitted\n", txs->txs_idx);
+ RALINK_DEBUG(RALINK_DEBUG_REG,"-tx(%d) transmitted\n",
+ txs->txs_idx);
SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 0,
- txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
+ txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
m_freem(txs->txs_mbuf);
txs->txs_mbuf = NULL;
@@ -1642,13 +1646,13 @@ ralink_eth_mii_read(device_t self, int p
#if defined(RT3050) || defined(RT3052)
sw_write(sc, RA_ETH_SW_PCTL0,
- PCTL0_RD_CMD | PCTL0_REG(phy_reg) | PCTL0_ADDR(phy_addr));
+ PCTL0_RD_CMD | PCTL0_REG(phy_reg) | PCTL0_ADDR(phy_addr));
#else
fe_write(sc, RA_FE_MDIO_ACCESS,
- MDIO_ACCESS_PHY_ADDR(phy_addr) | MDIO_ACCESS_REG(phy_reg));
+ MDIO_ACCESS_PHY_ADDR(phy_addr) | MDIO_ACCESS_REG(phy_reg));
fe_write(sc, RA_FE_MDIO_ACCESS,
- MDIO_ACCESS_PHY_ADDR(phy_addr) | MDIO_ACCESS_REG(phy_reg) |
- MDIO_ACCESS_TRG);
+ MDIO_ACCESS_PHY_ADDR(phy_addr) | MDIO_ACCESS_REG(phy_reg) |
+ MDIO_ACCESS_TRG);
#endif
/*
@@ -1659,14 +1663,14 @@ ralink_eth_mii_read(device_t self, int p
#if defined(RT3050) || defined(RT3052)
if ((sw_read(sc, RA_ETH_SW_PCTL1) & PCTL1_RD_DONE) != 0) {
int data = PCTL1_RD_VAL(
- sw_read(sc, RA_ETH_SW_PCTL1));
+ sw_read(sc, RA_ETH_SW_PCTL1));
ralink_eth_mdio_enable(sc, false);
return data;
}
#else
if ((fe_read(sc, RA_FE_MDIO_ACCESS) & MDIO_ACCESS_TRG) == 0) {
int data = MDIO_ACCESS_DATA(
- fe_read(sc, RA_FE_MDIO_ACCESS));
+ fe_read(sc, RA_FE_MDIO_ACCESS));
ralink_eth_mdio_enable(sc, false);
return data;
}
@@ -1684,7 +1688,7 @@ ralink_eth_mii_write(device_t self, int
KASSERT(sc != NULL);
#if 0
printf("%s() phy_addr: %d phy_reg: %d val: 0x%04x\n",
- __func__, phy_addr, phy_reg, val);
+ __func__, phy_addr, phy_reg, val);
#endif
ralink_eth_mdio_enable(sc, true);
@@ -1704,16 +1708,16 @@ ralink_eth_mii_write(device_t self, int
#if defined(RT3050) || defined(RT3052)
sw_write(sc, RA_ETH_SW_PCTL0,
- PCTL0_WR_CMD | PCTL0_WR_VAL(val) | PCTL0_REG(phy_reg) |
- PCTL0_ADDR(phy_addr));
+ PCTL0_WR_CMD | PCTL0_WR_VAL(val) | PCTL0_REG(phy_reg) |
+ PCTL0_ADDR(phy_addr));
#else
fe_write(sc, RA_FE_MDIO_ACCESS,
- MDIO_ACCESS_WR | MDIO_ACCESS_PHY_ADDR(phy_addr) |
- MDIO_ACCESS_REG(phy_reg) | MDIO_ACCESS_DATA(val));
+ MDIO_ACCESS_WR | MDIO_ACCESS_PHY_ADDR(phy_addr) |
+ MDIO_ACCESS_REG(phy_reg) | MDIO_ACCESS_DATA(val));
fe_write(sc, RA_FE_MDIO_ACCESS,
- MDIO_ACCESS_WR | MDIO_ACCESS_PHY_ADDR(phy_addr) |
- MDIO_ACCESS_REG(phy_reg) | MDIO_ACCESS_DATA(val) |
- MDIO_ACCESS_TRG);
+ MDIO_ACCESS_WR | MDIO_ACCESS_PHY_ADDR(phy_addr) |
+ MDIO_ACCESS_REG(phy_reg) | MDIO_ACCESS_DATA(val) |
+ MDIO_ACCESS_TRG);
#endif
Index: src/sys/arch/mips/ralink/ralink_reg.h
diff -u src/sys/arch/mips/ralink/ralink_reg.h:1.7 src/sys/arch/mips/ralink/ralink_reg.h:1.8
--- src/sys/arch/mips/ralink/ralink_reg.h:1.7 Wed Apr 30 00:53:31 2014
+++ src/sys/arch/mips/ralink/ralink_reg.h Wed Oct 5 15:39:31 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: ralink_reg.h,v 1.7 2014/04/30 00:53:31 matt Exp $ */
+/* $NetBSD: ralink_reg.h,v 1.8 2016/10/05 15:39:31 ryo Exp $ */
/*-
* Copyright (c) 2011 CradlePoint Technology, Inc.
* All rights reserved.
@@ -44,7 +44,7 @@
#define RA_BUS_FREQ (RA_CLOCK_RATE / 3)
#define RA_UART_FREQ RA_BUS_FREQ
#elif defined(RT3052)
-#define RA_CLOCK_RATE 384000000
+#define RA_CLOCK_RATE 384000000
#define RA_BUS_FREQ (RA_CLOCK_RATE / 3)
#define RA_UART_FREQ RA_BUS_FREQ
#elif defined(RT3883)
@@ -85,7 +85,7 @@
#elif defined(RT3883)
#define RA_FLASHCTL_BASE 0x10000700
#endif
-#define RA_NANDCTL_BASE 0x10000800
+#define RA_NANDCTL_BASE 0x10000800
#define RA_I2C_BASE 0x10000900
#define RA_I2S_BASE 0x10000A00
#define RA_SPI_BASE 0x10000B00
@@ -126,8 +126,8 @@
#define RA_IOREG_VADDR(base, offset) \
(volatile uint32_t *)MIPS_PHYS_TO_KSEG1((base) + (offset))
-#define FLD_GET(val,pos,mask) (((val) >> (pos)) & (mask))
-#define FLD_SET(val,pos,mask) (((val) & (mask)) << (pos))
+#define FLD_GET(val,pos,mask) (((val) >> (pos)) & (mask))
+#define FLD_SET(val,pos,mask) (((val) & (mask)) << (pos))
/*
* System Control Registers
@@ -144,19 +144,19 @@
#define RA_SYSCTL_GPIOMODE 0x60
#if defined(RT3050) || defined(RT3052)
-#define SYSCTL_CFG0_INIC_EE_SDRAM __BIT(29)
-#define SYSCTL_CFG0_INIC_8MB_SDRAM __BIT(28)
+#define SYSCTL_CFG0_INIC_EE_SDRAM __BIT(29)
+#define SYSCTL_CFG0_INIC_8MB_SDRAM __BIT(28)
#define SYSCTL_CFG0_GE0_MODE __BITS(24,25)
#define SYSCTL_CFG0_BYPASS_PLL __BIT(21)
#define SYSCTL_CFG0_BE __BIT(20)
-#define SYSCTL_CFG0_CPU_CLK_SEL __BIT(18)
+#define SYSCTL_CFG0_CPU_CLK_SEL __BIT(18)
#define SYSCTL_CFG0_BOOT_FROM __BITS(16,17)
#define SYSCTL_CFG0_TEST_CODE __BITS(8,15)
#define SYSCTL_CFG0_SRAM_CS_MODE __BITS(2,3)
#define SYSCTL_CFG0_SDRAM_CLK_DRV __BIT(0)
#elif defined(RT3883)
#define SYSCTL_CFG0_BE __BIT(19)
-#define SYSCTL_CFG0_DRAM_SIZE __BITS(12,14)
+#define SYSCTL_CFG0_DRAM_SIZE __BITS(12,14)
#define SYSCTL_CFG0_DRAM_2MB 0
#define SYSCTL_CFG0_DRAM_8MB 1
#define SYSCTL_CFG0_DRAM_16MB 2
@@ -203,7 +203,7 @@
#define SYSCTL_CLKCFG0_INT_CLK_FFRAC __BITS(16,12)
#define SYSCTL_CLKCFG0_PERI_CLK_SEL __BIT(4)
#define SYSCTL_CLKCFG0_EPHY_USE_25M __BIT(3)
-#endif
+#endif
#if defined(RT3883)
#define SYSCTL_CLKCFG1_PBUS_DIV2 __BIT(30)
@@ -391,115 +391,113 @@
/*
* General Purpose I/O
*/
-#define RA_PIO_00_23_INT 0x00
-#define RA_PIO_00_23_EDGE_INT 0x04
-#define RA_PIO_00_23_INT_RISE_EN 0x08
-#define RA_PIO_00_23_INT_FALL_EN 0x0C
-#define RA_PIO_00_23_DATA 0x20
-#define RA_PIO_00_23_DIR 0x24
-#define RA_PIO_00_23_POLARITY 0x28
-#define RA_PIO_00_23_SET_BIT 0x2C
-#define RA_PIO_00_23_CLR_BIT 0x30
-#define RA_PIO_00_23_TGL_BIT 0x34
-#define RA_PIO_24_39_INT 0x38
-#define RA_PIO_24_39_EDGE_INT 0x3C
-#define RA_PIO_24_39_INT_RISE_EN 0x40
-#define RA_PIO_24_39_INT_FALL_EN 0x44
-#define RA_PIO_24_39_DATA 0x48
-#define RA_PIO_24_39_DIR 0x4C
-#define RA_PIO_24_39_POLARITY 0x50
-#define RA_PIO_24_39_SET_BIT 0x54
-#define RA_PIO_24_39_CLR_BIT 0x58
-#define RA_PIO_24_39_TGL_BIT 0x5C
-#define RA_PIO_40_51_INT 0x60
-#define RA_PIO_40_51_EDGE_INT 0x64
-#define RA_PIO_40_51_INT_RISE_EN 0x68
-#define RA_PIO_40_51_INT_FALL_EN 0x6C
-#define RA_PIO_40_51_DATA 0x70
-#define RA_PIO_40_51_DIR 0x74
-#define RA_PIO_40_51_POLARITY 0x78
-#define RA_PIO_40_51_SET_BIT 0x7C
-#define RA_PIO_40_51_CLR_BIT 0x80
-#define RA_PIO_40_51_TGL_BIT 0x84
-#define RA_PIO_72_95_INT 0x88
-#define RA_PIO_72_95_EDGE_INT 0x8c
-#define RA_PIO_72_95_INT_RISE_EN 0x90
-#define RA_PIO_72_95_INT_FALL_EN 0x94
-#define RA_PIO_72_95_DATA 0x98
-#define RA_PIO_72_95_DIR 0x9c
-#define RA_PIO_72_95_POLARITY 0xa0
-#define RA_PIO_72_95_SET_BIT 0xa4
-#define RA_PIO_72_95_CLR_BIT 0xa8
-#define RA_PIO_72_95_TGL_BIT 0xac
+#define RA_PIO_00_23_INT 0x00
+#define RA_PIO_00_23_EDGE_INT 0x04
+#define RA_PIO_00_23_INT_RISE_EN 0x08
+#define RA_PIO_00_23_INT_FALL_EN 0x0C
+#define RA_PIO_00_23_DATA 0x20
+#define RA_PIO_00_23_DIR 0x24
+#define RA_PIO_00_23_POLARITY 0x28
+#define RA_PIO_00_23_SET_BIT 0x2C
+#define RA_PIO_00_23_CLR_BIT 0x30
+#define RA_PIO_00_23_TGL_BIT 0x34
+#define RA_PIO_24_39_INT 0x38
+#define RA_PIO_24_39_EDGE_INT 0x3C
+#define RA_PIO_24_39_INT_RISE_EN 0x40
+#define RA_PIO_24_39_INT_FALL_EN 0x44
+#define RA_PIO_24_39_DATA 0x48
+#define RA_PIO_24_39_DIR 0x4C
+#define RA_PIO_24_39_POLARITY 0x50
+#define RA_PIO_24_39_SET_BIT 0x54
+#define RA_PIO_24_39_CLR_BIT 0x58
+#define RA_PIO_24_39_TGL_BIT 0x5C
+#define RA_PIO_40_51_INT 0x60
+#define RA_PIO_40_51_EDGE_INT 0x64
+#define RA_PIO_40_51_INT_RISE_EN 0x68
+#define RA_PIO_40_51_INT_FALL_EN 0x6C
+#define RA_PIO_40_51_DATA 0x70
+#define RA_PIO_40_51_DIR 0x74
+#define RA_PIO_40_51_POLARITY 0x78
+#define RA_PIO_40_51_SET_BIT 0x7C
+#define RA_PIO_40_51_CLR_BIT 0x80
+#define RA_PIO_40_51_TGL_BIT 0x84
+#define RA_PIO_72_95_INT 0x88
+#define RA_PIO_72_95_EDGE_INT 0x8c
+#define RA_PIO_72_95_INT_RISE_EN 0x90
+#define RA_PIO_72_95_INT_FALL_EN 0x94
+#define RA_PIO_72_95_DATA 0x98
+#define RA_PIO_72_95_DIR 0x9c
+#define RA_PIO_72_95_POLARITY 0xa0
+#define RA_PIO_72_95_SET_BIT 0xa4
+#define RA_PIO_72_95_CLR_BIT 0xa8
+#define RA_PIO_72_95_TGL_BIT 0xac
/*
* UART registers
*/
-#define RA_UART_RBR 0x00
-#define RA_UART_TBR 0x04
-#define RA_UART_IER 0x08
-#define RA_UART_IIR 0x0C
-#define RA_UART_FCR 0x10
-#define RA_UART_LCR 0x14
-#define RA_UART_MCR 0x18
-#define RA_UART_LSR 0x1C
-#define RA_UART_MSR 0x20
-#define RA_UART_DLL 0x28
-
-
-#define UART_IER_ELSI __BIT(2)
- /* Receiver Line Status Interrupt Enable */
-#define UART_IER_ETBEI __BIT(1)
- /* Transmit Buffer Empty Interrupt Enable */
+#define RA_UART_RBR 0x00
+#define RA_UART_TBR 0x04
+#define RA_UART_IER 0x08
+#define RA_UART_IIR 0x0C
+#define RA_UART_FCR 0x10
+#define RA_UART_LCR 0x14
+#define RA_UART_MCR 0x18
+#define RA_UART_LSR 0x1C
+#define RA_UART_MSR 0x20
+#define RA_UART_DLL 0x28
+
+
+#define UART_IER_ELSI __BIT(2) /* Receiver Line Status Interrupt Enable */
+#define UART_IER_ETBEI __BIT(1) /* Transmit Buffer Empty Interrupt Enable */
#define UART_IER_ERBFI __BIT(0)
- /* Data Ready or Character Time-Out Interrupt Enable */
+ /* Data Ready or Character Time-Out Interrupt Enable */
-#define UART_IIR_FIFOES1 __BIT(7) /* FIFO Mode Enable Status */
-#define UART_IIR_FIFOES0 __BIT(6) /* FIFO Mode Enable Status */
-#define UART_IIR_IID3 __BIT(3) /* Interrupt Source Encoded */
-#define UART_IIR_IID2 __BIT(2) /* Interrupt Source Encoded */
-#define UART_IIR_IID1 __BIT(1) /* Interrupt Source Encoded */
-#define UART_IIR_IP __BIT(0) /* Interrupt Pending (active low) */
-
-#define UART_FCR_RXTRIG1 __BIT(7) /* Receiver Interrupt Trigger Level */
-#define UART_FCR_RXTRIG0 __BIT(6) /* Receiver Interrupt Trigger Level */
-#define UART_FCR_TXTRIG1 __BIT(5) /* Transmitter Interrupt Trigger Level */
-#define UART_FCR_TXTRIG0 __BIT(4) /* Transmitter Interrupt Trigger Level */
-#define UART_FCR_DMAMODE __BIT(3) /* Enable DMA transfers */
-#define UART_FCR_TXRST __BIT(2) /* Reset Transmitter FIFO */
-#define UART_FCR_RXRST __BIT(1) /* Reset Receiver FIFO */
-#define UART_FCR_FIFOE __BIT(0) /* Transmit and Receive FIFO Enable */
-
-#define UART_LCR_DLAB __BIT(7) /* Divisor Latch Access Bit */
-#define UART_LCR_SB __BIT(6) /* Set Break */
-#define UART_LCR_STKYP __BIT(5) /* Sticky Parity */
-#define UART_LCR_EPS __BIT(4) /* Even Parity Select */
-#define UART_LCR_PEN __BIT(3) /* Parity Enable */
-#define UART_LCR_STB __BIT(2) /* Stop Bit */
-#define UART_LCR_WLS1 __BIT(1) /* Word Length Select */
-#define UART_LCR_WLS0 __BIT(0) /* Word Length Select */
-
-#define UART_MCR_LOOP __BIT(4) /* Loop-back Mode Enable */
-
-#define UART_MSR_DCD __BIT(7) /* Data Carrier Detect */
-#define UART_MSR_RI __BIT(6) /* Ring Indicator */
-#define UART_MSR_DSR __BIT(5) /* Data Set Ready */
-#define UART_MSR_CTS __BIT(4) /* Clear To Send */
-#define UART_MSR_DDCD __BIT(3) /* Delta Data Carrier Detect */
-#define UART_MSR_TERI __BIT(2) /* Trailing Edge Ring Indicator */
-#define UART_MSR_DDSR __BIT(1) /* Delta Data Set Ready */
-#define UART_MSR_DCTS __BIT(0) /* Delta Clear To Send */
-
-#define UART_LSR_FIFOE __BIT(7) /* FIFO Error Status */
-#define UART_LSR_TEMT __BIT(6) /* Transmitter Empty */
-#define UART_LSR_TDRQ __BIT(5) /* Transmit Data Request */
-#define UART_LSR_BI __BIT(4) /* Break Interrupt */
-#define UART_LSR_FE __BIT(3) /* Framing Error */
-#define UART_LSR_PE __BIT(2) /* Parity Error */
-#define UART_LSR_OE __BIT(1) /* Overrun Error */
-#define UART_LSR_DR __BIT(0) /* Data Ready */
+#define UART_IIR_FIFOES1 __BIT(7) /* FIFO Mode Enable Status */
+#define UART_IIR_FIFOES0 __BIT(6) /* FIFO Mode Enable Status */
+#define UART_IIR_IID3 __BIT(3) /* Interrupt Source Encoded */
+#define UART_IIR_IID2 __BIT(2) /* Interrupt Source Encoded */
+#define UART_IIR_IID1 __BIT(1) /* Interrupt Source Encoded */
+#define UART_IIR_IP __BIT(0) /* Interrupt Pending (active low) */
+
+#define UART_FCR_RXTRIG1 __BIT(7) /* Receiver Interrupt Trigger Level */
+#define UART_FCR_RXTRIG0 __BIT(6) /* Receiver Interrupt Trigger Level */
+#define UART_FCR_TXTRIG1 __BIT(5) /* Transmitter Interrupt Trigger Level */
+#define UART_FCR_TXTRIG0 __BIT(4) /* Transmitter Interrupt Trigger Level */
+#define UART_FCR_DMAMODE __BIT(3) /* Enable DMA transfers */
+#define UART_FCR_TXRST __BIT(2) /* Reset Transmitter FIFO */
+#define UART_FCR_RXRST __BIT(1) /* Reset Receiver FIFO */
+#define UART_FCR_FIFOE __BIT(0) /* Transmit and Receive FIFO Enable */
+
+#define UART_LCR_DLAB __BIT(7) /* Divisor Latch Access Bit */
+#define UART_LCR_SB __BIT(6) /* Set Break */
+#define UART_LCR_STKYP __BIT(5) /* Sticky Parity */
+#define UART_LCR_EPS __BIT(4) /* Even Parity Select */
+#define UART_LCR_PEN __BIT(3) /* Parity Enable */
+#define UART_LCR_STB __BIT(2) /* Stop Bit */
+#define UART_LCR_WLS1 __BIT(1) /* Word Length Select */
+#define UART_LCR_WLS0 __BIT(0) /* Word Length Select */
+
+#define UART_MCR_LOOP __BIT(4) /* Loop-back Mode Enable */
+
+#define UART_MSR_DCD __BIT(7) /* Data Carrier Detect */
+#define UART_MSR_RI __BIT(6) /* Ring Indicator */
+#define UART_MSR_DSR __BIT(5) /* Data Set Ready */
+#define UART_MSR_CTS __BIT(4) /* Clear To Send */
+#define UART_MSR_DDCD __BIT(3) /* Delta Data Carrier Detect */
+#define UART_MSR_TERI __BIT(2) /* Trailing Edge Ring Indicator */
+#define UART_MSR_DDSR __BIT(1) /* Delta Data Set Ready */
+#define UART_MSR_DCTS __BIT(0) /* Delta Clear To Send */
+
+#define UART_LSR_FIFOE __BIT(7) /* FIFO Error Status */
+#define UART_LSR_TEMT __BIT(6) /* Transmitter Empty */
+#define UART_LSR_TDRQ __BIT(5) /* Transmit Data Request */
+#define UART_LSR_BI __BIT(4) /* Break Interrupt */
+#define UART_LSR_FE __BIT(3) /* Framing Error */
+#define UART_LSR_PE __BIT(2) /* Parity Error */
+#define UART_LSR_OE __BIT(1) /* Overrun Error */
+#define UART_LSR_DR __BIT(0) /* Data Ready */
/*
* I2C registers
@@ -514,18 +512,18 @@
#define RA_I2C_STARTXFR 0x1C
#define RA_I2C_BYTECNT 0x20
-#define I2C_CONFIG_ADDRLEN(x) (((x) & 0x7) << 5)
-#define I2C_CONFIG_ADDRLEN_7 6
-#define I2C_CONFIG_ADDRLEN_8 7
-#define I2C_CONFIG_DEVADLEN(x) (((x) & 0x7) << 2)
-#define I2C_CONFIG_DEVADLEN_6 5
-#define I2C_CONFIG_DEVADLEN_7 6
+#define I2C_CONFIG_ADDRLEN(x) (((x) & 0x7) << 5)
+#define I2C_CONFIG_ADDRLEN_7 6
+#define I2C_CONFIG_ADDRLEN_8 7
+#define I2C_CONFIG_DEVADLEN(x) (((x) & 0x7) << 2)
+#define I2C_CONFIG_DEVADLEN_6 5
+#define I2C_CONFIG_DEVADLEN_7 6
#define I2C_CONFIG_ADDRDIS __BIT(1)
#define I2C_CONFIG_DEVDIS __BIT(0)
-#define I2C_STATUS_STARTERR __BIT(4)
+#define I2C_STATUS_STARTERR __BIT(4)
#define I2C_STATUS_ACKERR __BIT(3)
#define I2C_STATUS_DATARDY __BIT(2)
-#define I2C_STATUS_SDOEMPTY __BIT(1)
+#define I2C_STATUS_SDOEMPTY __BIT(1)
#define I2C_STATUS_BUSY __BIT(0)
/*
@@ -538,264 +536,264 @@
#define SPI_STATUS_BUSY __BIT(0)
#define SPI_CONFIG_MSBFIRST __BIT(8)
-#define SPI_CONFIG_CLK __BIT(6)
+#define SPI_CONFIG_CLK __BIT(6)
#define SPI_CONFIG_RXCLKEDGE_FALL __BIT(5)
#define SPI_CONFIG_TXCLKEDGE_FALL __BIT(4)
#define SPI_CONFIG_TRISTATE __BIT(3)
#define SPI_CONFIG_RATE(x) ((x) & 0x7)
-#define SPI_CONFIG_RATE_DIV_2 0
-#define SPI_CONFIG_RATE_DIV_4 1
-#define SPI_CONFIG_RATE_DIV_8 2
-#define SPI_CONFIG_RATE_DIV_16 3
-#define SPI_CONFIG_RATE_DIV_32 4
-#define SPI_CONFIG_RATE_DIV_64 5
-#define SPI_CONFIG_RATE_DIV_128 6
-#define SPI_CONFIG_RATE_DIV_NONE 7
-#define SPI_CONTROL_TRISTATE __BIT(3)
+#define SPI_CONFIG_RATE_DIV_2 0
+#define SPI_CONFIG_RATE_DIV_4 1
+#define SPI_CONFIG_RATE_DIV_8 2
+#define SPI_CONFIG_RATE_DIV_16 3
+#define SPI_CONFIG_RATE_DIV_32 4
+#define SPI_CONFIG_RATE_DIV_64 5
+#define SPI_CONFIG_RATE_DIV_128 6
+#define SPI_CONFIG_RATE_DIV_NONE 7
+#define SPI_CONTROL_TRISTATE __BIT(3)
#define SPI_CONTROL_STARTWR __BIT(2)
#define SPI_CONTROL_STARTRD __BIT(1)
-#define SPI_CONTROL_ENABLE_LOW (0 << 0)
+#define SPI_CONTROL_ENABLE_LOW (0 << 0)
#define SPI_CONTROL_ENABLE_HIGH __BIT(0)
-#define SPI_DATA_VAL(x) ((x) & 0xff)
+#define SPI_DATA_VAL(x) ((x) & 0xff)
/*
* Frame Engine registers
*/
-#define RA_FE_MDIO_ACCESS 0x000
-#define RA_FE_MDIO_CFG1 0x004
-#define RA_FE_GLOBAL_CFG 0x008
-#define RA_FE_GLOBAL_RESET 0x00C
-#define RA_FE_INT_STATUS 0x010
-#define RA_FE_INT_ENABLE 0x014
-#define RA_FE_MDIO_CFG2 0x018
-#define RA_FE_TIME_STAMP 0x01C
-#define RA_FE_GDMA1_FWD_CFG 0x020
-#define RA_FE_GDMA1_SCHED_CFG 0x024
-#define RA_FE_GDMA1_SHAPE_CFG 0x028
-#define RA_FE_GDMA1_MAC_LSB 0x02C
-#define RA_FE_GDMA1_MAC_MSB 0x030
-#define RA_FE_PSE_FQ_CFG 0x040
-#define RA_FE_CDMA_FC_CFG 0x044
-#define RA_FE_GDMA1_FC_CFG 0x048
-#define RA_FE_GDMA2_FC_CFG 0x04C
-#define RA_FE_CDMA_OQ_STA 0x050
-#define RA_FE_GDMA1_OQ_STA 0x054
-#define RA_FE_GDMA2_OQ_STA 0x058
-#define RA_FE_PSE_IQ_STA 0x05C
-#define RA_FE_GDMA2_FWD_CFG 0x060
-#define RA_FE_GDMA2_SCHED_CFG 0x064
-#define RA_FE_GDMA2_SHAPE_CFG 0x068
-#define RA_FE_GDMA2_MAC_LSB 0x06C
-#define RA_FE_GDMA2_MAC_MSB 0x070
-#define RA_FE_CDMA_CSG_CFG 0x080
-#define RA_FE_CDMA_SCHED_CFG 0x084
-#define RA_FE_PPPOE_SID_0001 0x088
-#define RA_FE_PPPOE_SID_0203 0x08C
-#define RA_FE_PPPOE_SID_0405 0x090
-#define RA_FE_PPPOE_SID_0607 0x094
-#define RA_FE_PPPOE_SID_0809 0x098
-#define RA_FE_PPPOE_SID_1011 0x09C
-#define RA_FE_PPPOE_SID_1213 0x0A0
-#define RA_FE_PPPOE_SID_1415 0x0A4
-#define RA_FE_VLAN_ID_0001 0x0A8
-#define RA_FE_VLAN_ID_0203 0x0AC
-#define RA_FE_VLAN_ID_0405 0x0B0
-#define RA_FE_VLAN_ID_0607 0x0B4
-#define RA_FE_VLAN_ID_0809 0x0B8
-#define RA_FE_VLAN_ID_1011 0x0BC
-#define RA_FE_VLAN_ID_1213 0x0C0
-#define RA_FE_VLAN_ID_1415 0x0C4
-#define RA_FE_PDMA_GLOBAL_CFG 0x100
-#define RA_FE_PDMA_RESET_IDX 0x104
-#define RA_FE_PDMA_SCHED_CFG 0x108
-#define RA_FE_PDMA_DLY_INT_CFG 0x10C
-#define RA_FE_PDMA_TX0_PTR 0x110
-#define RA_FE_PDMA_TX0_COUNT 0x114
-#define RA_FE_PDMA_TX0_CPU_IDX 0x118
-#define RA_FE_PDMA_TX0_DMA_IDX 0x11C
-#define RA_FE_PDMA_TX1_PTR 0x120
-#define RA_FE_PDMA_TX1_COUNT 0x124
-#define RA_FE_PDMA_TX1_CPU_IDX 0x128
-#define RA_FE_PDMA_TX1_DMA_IDX 0x12C
-#define RA_FE_PDMA_RX0_PTR 0x130
-#define RA_FE_PDMA_RX0_COUNT 0x134
-#define RA_FE_PDMA_RX0_CPU_IDX 0x138
-#define RA_FE_PDMA_RX0_DMA_IDX 0x13C
-#define RA_FE_PDMA_TX2_PTR 0x140
-#define RA_FE_PDMA_TX2_COUNT 0x144
-#define RA_FE_PDMA_TX2_CPU_IDX 0x148
-#define RA_FE_PDMA_TX2_DMA_IDX 0x14C
-#define RA_FE_PDMA_TX3_PTR 0x150
-#define RA_FE_PDMA_TX3_COUNT 0x154
-#define RA_FE_PDMA_TX3_CPU_IDX 0x158
-#define RA_FE_PDMA_TX3_DMA_IDX 0x15C
-#define RA_FE_PDMA_FC_CFG 0x1F0
+#define RA_FE_MDIO_ACCESS 0x000
+#define RA_FE_MDIO_CFG1 0x004
+#define RA_FE_GLOBAL_CFG 0x008
+#define RA_FE_GLOBAL_RESET 0x00C
+#define RA_FE_INT_STATUS 0x010
+#define RA_FE_INT_ENABLE 0x014
+#define RA_FE_MDIO_CFG2 0x018
+#define RA_FE_TIME_STAMP 0x01C
+#define RA_FE_GDMA1_FWD_CFG 0x020
+#define RA_FE_GDMA1_SCHED_CFG 0x024
+#define RA_FE_GDMA1_SHAPE_CFG 0x028
+#define RA_FE_GDMA1_MAC_LSB 0x02C
+#define RA_FE_GDMA1_MAC_MSB 0x030
+#define RA_FE_PSE_FQ_CFG 0x040
+#define RA_FE_CDMA_FC_CFG 0x044
+#define RA_FE_GDMA1_FC_CFG 0x048
+#define RA_FE_GDMA2_FC_CFG 0x04C
+#define RA_FE_CDMA_OQ_STA 0x050
+#define RA_FE_GDMA1_OQ_STA 0x054
+#define RA_FE_GDMA2_OQ_STA 0x058
+#define RA_FE_PSE_IQ_STA 0x05C
+#define RA_FE_GDMA2_FWD_CFG 0x060
+#define RA_FE_GDMA2_SCHED_CFG 0x064
+#define RA_FE_GDMA2_SHAPE_CFG 0x068
+#define RA_FE_GDMA2_MAC_LSB 0x06C
+#define RA_FE_GDMA2_MAC_MSB 0x070
+#define RA_FE_CDMA_CSG_CFG 0x080
+#define RA_FE_CDMA_SCHED_CFG 0x084
+#define RA_FE_PPPOE_SID_0001 0x088
+#define RA_FE_PPPOE_SID_0203 0x08C
+#define RA_FE_PPPOE_SID_0405 0x090
+#define RA_FE_PPPOE_SID_0607 0x094
+#define RA_FE_PPPOE_SID_0809 0x098
+#define RA_FE_PPPOE_SID_1011 0x09C
+#define RA_FE_PPPOE_SID_1213 0x0A0
+#define RA_FE_PPPOE_SID_1415 0x0A4
+#define RA_FE_VLAN_ID_0001 0x0A8
+#define RA_FE_VLAN_ID_0203 0x0AC
+#define RA_FE_VLAN_ID_0405 0x0B0
+#define RA_FE_VLAN_ID_0607 0x0B4
+#define RA_FE_VLAN_ID_0809 0x0B8
+#define RA_FE_VLAN_ID_1011 0x0BC
+#define RA_FE_VLAN_ID_1213 0x0C0
+#define RA_FE_VLAN_ID_1415 0x0C4
+#define RA_FE_PDMA_GLOBAL_CFG 0x100
+#define RA_FE_PDMA_RESET_IDX 0x104
+#define RA_FE_PDMA_SCHED_CFG 0x108
+#define RA_FE_PDMA_DLY_INT_CFG 0x10C
+#define RA_FE_PDMA_TX0_PTR 0x110
+#define RA_FE_PDMA_TX0_COUNT 0x114
+#define RA_FE_PDMA_TX0_CPU_IDX 0x118
+#define RA_FE_PDMA_TX0_DMA_IDX 0x11C
+#define RA_FE_PDMA_TX1_PTR 0x120
+#define RA_FE_PDMA_TX1_COUNT 0x124
+#define RA_FE_PDMA_TX1_CPU_IDX 0x128
+#define RA_FE_PDMA_TX1_DMA_IDX 0x12C
+#define RA_FE_PDMA_RX0_PTR 0x130
+#define RA_FE_PDMA_RX0_COUNT 0x134
+#define RA_FE_PDMA_RX0_CPU_IDX 0x138
+#define RA_FE_PDMA_RX0_DMA_IDX 0x13C
+#define RA_FE_PDMA_TX2_PTR 0x140
+#define RA_FE_PDMA_TX2_COUNT 0x144
+#define RA_FE_PDMA_TX2_CPU_IDX 0x148
+#define RA_FE_PDMA_TX2_DMA_IDX 0x14C
+#define RA_FE_PDMA_TX3_PTR 0x150
+#define RA_FE_PDMA_TX3_COUNT 0x154
+#define RA_FE_PDMA_TX3_CPU_IDX 0x158
+#define RA_FE_PDMA_TX3_DMA_IDX 0x15C
+#define RA_FE_PDMA_FC_CFG 0x1F0
/* TODO: FE_COUNTERS */
-#define MDIO_ACCESS_TRG __BIT(31)
-#define MDIO_ACCESS_WR __BIT(30)
-#define MDIO_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 24)
-#define MDIO_ACCESS_REG(x) (((x) & 0x1f) << 16)
-#define MDIO_ACCESS_DATA(x) ((x) & 0xffff)
-#define MDIO_CFG_AUTO_POLL __BIT(29)
-#define MDIO_CFG_PHY_ADDR(x) (((x) & 0x1f) << 24)
-#define MDIO_CFG_BP_EN __BIT(16)
-#define MDIO_CFG_FORCE_CFG __BIT(15)
-#define MDIO_CFG_SPEED(x) (((x) & 0x3) << 13)
-#define MDIO_CFG_SPEED_1000M 2
-#define MDIO_CFG_SPEED_100M 1
-#define MDIO_CFG_SPEED_10M 0
-#define MDIO_CFG_FULL_DUPLEX __BIT(12)
-#define MDIO_CFG_FC_TX __BIT(11)
-#define MDIO_CFG_FC_RX __BIT(10)
-#define MDIO_CFG_LINK_DOWN __BIT(9)
-#define MDIO_CFG_AUTO_DONE __BIT(8)
-#define MDIO_CFG_MDC_CLKDIV(x) (((x) & 0x3) << 6)
-#define MDIO_CFG_MDC_512KHZ 3
-#define MDIO_CFG_MDC_1MHZ 2
-#define MDIO_CFG_MDC_2MHZ 1
-#define MDIO_CFG_MDC_4MHZ 0
-#define MDIO_CFG_TURBO_50MHZ __BIT(5)
-#define MDIO_CFG_TURBO_EN __BIT(4)
-#define MDIO_CFG_RX_CLK_SKEW (((x) & 0x3) << 2)
-#define MDIO_CFG_RX_SKEW_INV 3
-#define MDIO_CFG_RX_SKEW_400PS 2
-#define MDIO_CFG_RX_SKEW_200PS 1
-#define MDIO_CFG_RX_SKEW_ZERO 0
-#define MDIO_CFG_TX_CLK_MODE(x) (((x) & 0x1) << 0)
-#define MDIO_CFG_TX_CLK_MODE_3COM 1
-#define MDIO_CFG_TX_CLK_MODE_HP 0
-#define FE_GLOBAL_CFG_EXT_VLAN(x) (((x) & 0xffff) << 16)
-#define FE_GLOBAL_CFG_US_CLK(x) (((x) & 0xff) << 8)
-#define FE_GLOBAL_CFG_L2_SPACE(x) (((x) & 0xf) << 4)
-#define FE_GLOBAL_RESET_PSE __BIT(0)
-#define FE_INT_PPE_COUNT_HIGH __BIT(31)
-#define FE_INT_DMA_COUNT_HIGH __BIT(29)
-#define FE_INT_PSE_P2_FC_ASSERT __BIT(26)
-#define FE_INT_PSE_FC_DROP __BIT(24)
-#define FE_INT_GDMA_DROP_OTHER __BIT(23)
-#define FE_INT_PSE_P1_FC_ASSERT __BIT(22)
-#define FE_INT_PSE_P0_FC_ASSERT __BIT(21)
-#define FE_INT_PSE_FQ_EMPTY __BIT(20)
-#define FE_INT_TX_COHERENT __BIT(17)
-#define FE_INT_RX_COHERENT __BIT(16)
-#define FE_INT_TX3 __BIT(11)
-#define FE_INT_TX2 __BIT(10)
-#define FE_INT_TX1 __BIT(9)
-#define FE_INT_TX0 __BIT(8)
-#define FE_INT_RX __BIT(2)
-#define FE_INT_TX_DELAY __BIT(1)
-#define FE_INT_RX_DELAY __BIT(0)
-#define FE_GDMA_FWD_CFG_JUMBO_LEN(x) (((x) & 0xf) << 28)
-#define FE_GDMA_FWD_CFG_DROP_256B __BIT(23)
-#define FE_GDMA_FWD_CFG_IP4_CRC_EN __BIT(22)
-#define FE_GDMA_FWD_CFG_TCP_CRC_EN __BIT(21)
-#define FE_GDMA_FWD_CFG_UDP_CRC_EN __BIT(20)
-#define FE_GDMA_FWD_CFG_JUMBO_EN __BIT(19)
-#define FE_GDMA_FWD_CFG_DIS_TX_PAD __BIT(18)
-#define FE_GDMA_FWD_CFG_DIS_TX_CRC __BIT(17)
-#define FE_GDMA_FWD_CFG_STRIP_RX_CRC __BIT(16)
-#define FE_GDMA_FWD_CFG_UNICA_PORT(x) (((x) & 0x3) << 12)
-#define FE_GDMA_FWD_CFG_BROAD_PORT(x) (((x) & 0x3) << 8)
-#define FE_GDMA_FWD_CFG_MULTI_PORT(x) (((x) & 0x3) << 6)
-#define FE_GDMA_FWD_CFG_OTHER_PORT(x) (((x) & 0x3) << 0)
-#define FE_GDMA_FWD_CFG_PORT_DROP 7
-#define FE_GDMA_FWD_CFG_PORT_PPE 6
-#define FE_GDMA_FWD_CFG_PORT_GDMA2 2
-#define FE_GDMA_FWD_CFG_PORT_GDMA1 1
-#define FE_GDMA_FWD_CFG_PORT_CPU 0
-#define FE_PSE_FQ_MAX_COUNT(x) (((x) & 0xff) << 24)
-#define FE_PSE_FQ_FC_RELEASE(x) (((x) & 0xff) << 16)
-#define FE_PSE_FQ_FC_ASSERT(x) (((x) & 0xff) << 8)
-#define FE_PSE_FQ_FC_DROP(x) (((x) & 0xff) << 0)
-#define FE_CDMA_CSG_CFG_VLAN_TAG(x) (((x) & 0xffff) << 16)
-#define FE_CDMA_CSG_CFG_IP4_CRC_EN __BIT(2)
-#define FE_CDMA_CSG_CFG_UDP_CRC_EN __BIT(1)
-#define FE_CDMA_CSG_CFG_TCP_CRC_EN __BIT(0)
-#define FE_PDMA_GLOBAL_CFG_HDR_SEG_LEN __BIT(16)
-#define FE_PDMA_GLOBAL_CFG_TX_WB_DDONE __BIT(6)
-#define FE_PDMA_GLOBAL_CFG_BURST_SZ(x) (((x) & 0x3) << 4)
-#define FE_PDMA_GLOBAL_CFG_BURST_SZ_4 (0 << 4)
-#define FE_PDMA_GLOBAL_CFG_BURST_SZ_8 __BIT(4)
-#define FE_PDMA_GLOBAL_CFG_BURST_SZ_16 (2 << 4)
-#define FE_PDMA_GLOBAL_CFG_RX_DMA_BUSY __BIT(3)
-#define FE_PDMA_GLOBAL_CFG_RX_DMA_EN __BIT(2)
-#define FE_PDMA_GLOBAL_CFG_TX_DMA_BUSY __BIT(1)
-#define FE_PDMA_GLOBAL_CFG_TX_DMA_EN __BIT(0)
-#define PDMA_RST_RX0 __BIT(16)
-#define PDMA_RST_TX3 __BIT(3)
-#define PDMA_RST_TX2 __BIT(2)
-#define PDMA_RST_TX1 __BIT(1)
-#define PDMA_RST_TX0 __BIT(0)
+#define MDIO_ACCESS_TRG __BIT(31)
+#define MDIO_ACCESS_WR __BIT(30)
+#define MDIO_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 24)
+#define MDIO_ACCESS_REG(x) (((x) & 0x1f) << 16)
+#define MDIO_ACCESS_DATA(x) ((x) & 0xffff)
+#define MDIO_CFG_AUTO_POLL __BIT(29)
+#define MDIO_CFG_PHY_ADDR(x) (((x) & 0x1f) << 24)
+#define MDIO_CFG_BP_EN __BIT(16)
+#define MDIO_CFG_FORCE_CFG __BIT(15)
+#define MDIO_CFG_SPEED(x) (((x) & 0x3) << 13)
+#define MDIO_CFG_SPEED_1000M 2
+#define MDIO_CFG_SPEED_100M 1
+#define MDIO_CFG_SPEED_10M 0
+#define MDIO_CFG_FULL_DUPLEX __BIT(12)
+#define MDIO_CFG_FC_TX __BIT(11)
+#define MDIO_CFG_FC_RX __BIT(10)
+#define MDIO_CFG_LINK_DOWN __BIT(9)
+#define MDIO_CFG_AUTO_DONE __BIT(8)
+#define MDIO_CFG_MDC_CLKDIV(x) (((x) & 0x3) << 6)
+#define MDIO_CFG_MDC_512KHZ 3
+#define MDIO_CFG_MDC_1MHZ 2
+#define MDIO_CFG_MDC_2MHZ 1
+#define MDIO_CFG_MDC_4MHZ 0
+#define MDIO_CFG_TURBO_50MHZ __BIT(5)
+#define MDIO_CFG_TURBO_EN __BIT(4)
+#define MDIO_CFG_RX_CLK_SKEW (((x) & 0x3) << 2)
+#define MDIO_CFG_RX_SKEW_INV 3
+#define MDIO_CFG_RX_SKEW_400PS 2
+#define MDIO_CFG_RX_SKEW_200PS 1
+#define MDIO_CFG_RX_SKEW_ZERO 0
+#define MDIO_CFG_TX_CLK_MODE(x) (((x) & 0x1) << 0)
+#define MDIO_CFG_TX_CLK_MODE_3COM 1
+#define MDIO_CFG_TX_CLK_MODE_HP 0
+#define FE_GLOBAL_CFG_EXT_VLAN(x) (((x) & 0xffff) << 16)
+#define FE_GLOBAL_CFG_US_CLK(x) (((x) & 0xff) << 8)
+#define FE_GLOBAL_CFG_L2_SPACE(x) (((x) & 0xf) << 4)
+#define FE_GLOBAL_RESET_PSE __BIT(0)
+#define FE_INT_PPE_COUNT_HIGH __BIT(31)
+#define FE_INT_DMA_COUNT_HIGH __BIT(29)
+#define FE_INT_PSE_P2_FC_ASSERT __BIT(26)
+#define FE_INT_PSE_FC_DROP __BIT(24)
+#define FE_INT_GDMA_DROP_OTHER __BIT(23)
+#define FE_INT_PSE_P1_FC_ASSERT __BIT(22)
+#define FE_INT_PSE_P0_FC_ASSERT __BIT(21)
+#define FE_INT_PSE_FQ_EMPTY __BIT(20)
+#define FE_INT_TX_COHERENT __BIT(17)
+#define FE_INT_RX_COHERENT __BIT(16)
+#define FE_INT_TX3 __BIT(11)
+#define FE_INT_TX2 __BIT(10)
+#define FE_INT_TX1 __BIT(9)
+#define FE_INT_TX0 __BIT(8)
+#define FE_INT_RX __BIT(2)
+#define FE_INT_TX_DELAY __BIT(1)
+#define FE_INT_RX_DELAY __BIT(0)
+#define FE_GDMA_FWD_CFG_JUMBO_LEN(x) (((x) & 0xf) << 28)
+#define FE_GDMA_FWD_CFG_DROP_256B __BIT(23)
+#define FE_GDMA_FWD_CFG_IP4_CRC_EN __BIT(22)
+#define FE_GDMA_FWD_CFG_TCP_CRC_EN __BIT(21)
+#define FE_GDMA_FWD_CFG_UDP_CRC_EN __BIT(20)
+#define FE_GDMA_FWD_CFG_JUMBO_EN __BIT(19)
+#define FE_GDMA_FWD_CFG_DIS_TX_PAD __BIT(18)
+#define FE_GDMA_FWD_CFG_DIS_TX_CRC __BIT(17)
+#define FE_GDMA_FWD_CFG_STRIP_RX_CRC __BIT(16)
+#define FE_GDMA_FWD_CFG_UNICA_PORT(x) (((x) & 0x3) << 12)
+#define FE_GDMA_FWD_CFG_BROAD_PORT(x) (((x) & 0x3) << 8)
+#define FE_GDMA_FWD_CFG_MULTI_PORT(x) (((x) & 0x3) << 6)
+#define FE_GDMA_FWD_CFG_OTHER_PORT(x) (((x) & 0x3) << 0)
+#define FE_GDMA_FWD_CFG_PORT_DROP 7
+#define FE_GDMA_FWD_CFG_PORT_PPE 6
+#define FE_GDMA_FWD_CFG_PORT_GDMA2 2
+#define FE_GDMA_FWD_CFG_PORT_GDMA1 1
+#define FE_GDMA_FWD_CFG_PORT_CPU 0
+#define FE_PSE_FQ_MAX_COUNT(x) (((x) & 0xff) << 24)
+#define FE_PSE_FQ_FC_RELEASE(x) (((x) & 0xff) << 16)
+#define FE_PSE_FQ_FC_ASSERT(x) (((x) & 0xff) << 8)
+#define FE_PSE_FQ_FC_DROP(x) (((x) & 0xff) << 0)
+#define FE_CDMA_CSG_CFG_VLAN_TAG(x) (((x) & 0xffff) << 16)
+#define FE_CDMA_CSG_CFG_IP4_CRC_EN __BIT(2)
+#define FE_CDMA_CSG_CFG_UDP_CRC_EN __BIT(1)
+#define FE_CDMA_CSG_CFG_TCP_CRC_EN __BIT(0)
+#define FE_PDMA_GLOBAL_CFG_HDR_SEG_LEN __BIT(16)
+#define FE_PDMA_GLOBAL_CFG_TX_WB_DDONE __BIT(6)
+#define FE_PDMA_GLOBAL_CFG_BURST_SZ(x) (((x) & 0x3) << 4)
+#define FE_PDMA_GLOBAL_CFG_BURST_SZ_4 (0 << 4)
+#define FE_PDMA_GLOBAL_CFG_BURST_SZ_8 __BIT(4)
+#define FE_PDMA_GLOBAL_CFG_BURST_SZ_16 (2 << 4)
+#define FE_PDMA_GLOBAL_CFG_RX_DMA_BUSY __BIT(3)
+#define FE_PDMA_GLOBAL_CFG_RX_DMA_EN __BIT(2)
+#define FE_PDMA_GLOBAL_CFG_TX_DMA_BUSY __BIT(1)
+#define FE_PDMA_GLOBAL_CFG_TX_DMA_EN __BIT(0)
+#define PDMA_RST_RX0 __BIT(16)
+#define PDMA_RST_TX3 __BIT(3)
+#define PDMA_RST_TX2 __BIT(2)
+#define PDMA_RST_TX1 __BIT(1)
+#define PDMA_RST_TX0 __BIT(0)
/*
* 10/100 Switch registers
*/
-#define RA_ETH_SW_ISR 0x00
-#define RA_ETH_SW_IMR 0x04
-#define RA_ETH_SW_FCT0 0x08
-#define RA_ETH_SW_FCT1 0x0C
-#define RA_ETH_SW_PFC0 0x10
-#define RA_ETH_SW_PFC1 0x14
-#define RA_ETH_SW_PFC2 0x18
-#define RA_ETH_SW_QCS0 0x1C
-#define RA_ETH_SW_QCS1 0x20
-#define RA_ETH_SW_ATS 0x24
-#define RA_ETH_SW_ATS0 0x28
-#define RA_ETH_SW_ATS1 0x2C
-#define RA_ETH_SW_ATS2 0x30
-#define RA_ETH_SW_WMAD0 0x34
-#define RA_ETH_SW_WMAD1 0x38
-#define RA_ETH_SW_WMAD2 0x3C
-#define RA_ETH_SW_PVIDC0 0x40
-#define RA_ETH_SW_PVIDC1 0x44
-#define RA_ETH_SW_PVIDC2 0x48
-#define RA_ETH_SW_PVIDC3 0x4C
-#define RA_ETH_SW_VLANI0 0x50
-#define RA_ETH_SW_VLANI1 0x54
-#define RA_ETH_SW_VLANI2 0x58
-#define RA_ETH_SW_VLANI3 0x5C
-#define RA_ETH_SW_VLANI4 0x60
-#define RA_ETH_SW_VLANI5 0x64
-#define RA_ETH_SW_VLANI6 0x68
-#define RA_ETH_SW_VLANI7 0x6C
-#define RA_ETH_SW_VMSC0 0x70
-#define RA_ETH_SW_VMSC1 0x74
-#define RA_ETH_SW_VMSC2 0x78
-#define RA_ETH_SW_VMSC3 0x7C
-#define RA_ETH_SW_POA 0x80
-#define RA_ETH_SW_FPA 0x84
-#define RA_ETH_SW_PTS 0x88
-#define RA_ETH_SW_SOCPC 0x8C
-#define RA_ETH_SW_POC0 0x90
-#define RA_ETH_SW_POC1 0x94
-#define RA_ETH_SW_POC2 0x98
-#define RA_ETH_SW_SWGC 0x9C
-#define RA_ETH_SW_RST 0xA0
-#define RA_ETH_SW_LEDP0 0xA4
-#define RA_ETH_SW_LEDP1 0xA8
-#define RA_ETH_SW_LEDP2 0xAC
-#define RA_ETH_SW_LEDP3 0xB0
-#define RA_ETH_SW_LEDP4 0xB4
-#define RA_ETH_SW_WDOG 0xB8
-#define RA_ETH_SW_DBG 0xBC
-#define RA_ETH_SW_PCTL0 0xC0
-#define RA_ETH_SW_PCTL1 0xC4
-#define RA_ETH_SW_FPORT 0xC8
-#define RA_ETH_SW_FTC2 0xCC
-#define RA_ETH_SW_QSS0 0xD0
-#define RA_ETH_SW_QSS1 0xD4
-#define RA_ETH_SW_DBGC 0xD8
-#define RA_ETH_SW_MTI1 0xDC
-#define RA_ETH_SW_PPC 0xE0
-#define RA_ETH_SW_SGC2 0xE4
-#define RA_ETH_SW_PCNT0 0xE8
-#define RA_ETH_SW_PCNT1 0xEC
-#define RA_ETH_SW_PCNT2 0xF0
-#define RA_ETH_SW_PCNT3 0xF4
-#define RA_ETH_SW_PCNT4 0xF8
-#define RA_ETH_SW_PCNT5 0xFC
+#define RA_ETH_SW_ISR 0x00
+#define RA_ETH_SW_IMR 0x04
+#define RA_ETH_SW_FCT0 0x08
+#define RA_ETH_SW_FCT1 0x0C
+#define RA_ETH_SW_PFC0 0x10
+#define RA_ETH_SW_PFC1 0x14
+#define RA_ETH_SW_PFC2 0x18
+#define RA_ETH_SW_QCS0 0x1C
+#define RA_ETH_SW_QCS1 0x20
+#define RA_ETH_SW_ATS 0x24
+#define RA_ETH_SW_ATS0 0x28
+#define RA_ETH_SW_ATS1 0x2C
+#define RA_ETH_SW_ATS2 0x30
+#define RA_ETH_SW_WMAD0 0x34
+#define RA_ETH_SW_WMAD1 0x38
+#define RA_ETH_SW_WMAD2 0x3C
+#define RA_ETH_SW_PVIDC0 0x40
+#define RA_ETH_SW_PVIDC1 0x44
+#define RA_ETH_SW_PVIDC2 0x48
+#define RA_ETH_SW_PVIDC3 0x4C
+#define RA_ETH_SW_VLANI0 0x50
+#define RA_ETH_SW_VLANI1 0x54
+#define RA_ETH_SW_VLANI2 0x58
+#define RA_ETH_SW_VLANI3 0x5C
+#define RA_ETH_SW_VLANI4 0x60
+#define RA_ETH_SW_VLANI5 0x64
+#define RA_ETH_SW_VLANI6 0x68
+#define RA_ETH_SW_VLANI7 0x6C
+#define RA_ETH_SW_VMSC0 0x70
+#define RA_ETH_SW_VMSC1 0x74
+#define RA_ETH_SW_VMSC2 0x78
+#define RA_ETH_SW_VMSC3 0x7C
+#define RA_ETH_SW_POA 0x80
+#define RA_ETH_SW_FPA 0x84
+#define RA_ETH_SW_PTS 0x88
+#define RA_ETH_SW_SOCPC 0x8C
+#define RA_ETH_SW_POC0 0x90
+#define RA_ETH_SW_POC1 0x94
+#define RA_ETH_SW_POC2 0x98
+#define RA_ETH_SW_SWGC 0x9C
+#define RA_ETH_SW_RST 0xA0
+#define RA_ETH_SW_LEDP0 0xA4
+#define RA_ETH_SW_LEDP1 0xA8
+#define RA_ETH_SW_LEDP2 0xAC
+#define RA_ETH_SW_LEDP3 0xB0
+#define RA_ETH_SW_LEDP4 0xB4
+#define RA_ETH_SW_WDOG 0xB8
+#define RA_ETH_SW_DBG 0xBC
+#define RA_ETH_SW_PCTL0 0xC0
+#define RA_ETH_SW_PCTL1 0xC4
+#define RA_ETH_SW_FPORT 0xC8
+#define RA_ETH_SW_FTC2 0xCC
+#define RA_ETH_SW_QSS0 0xD0
+#define RA_ETH_SW_QSS1 0xD4
+#define RA_ETH_SW_DBGC 0xD8
+#define RA_ETH_SW_MTI1 0xDC
+#define RA_ETH_SW_PPC 0xE0
+#define RA_ETH_SW_SGC2 0xE4
+#define RA_ETH_SW_PCNT0 0xE8
+#define RA_ETH_SW_PCNT1 0xEC
+#define RA_ETH_SW_PCNT2 0xF0
+#define RA_ETH_SW_PCNT3 0xF4
+#define RA_ETH_SW_PCNT4 0xF8
+#define RA_ETH_SW_PCNT5 0xFC
#define ISR_WDOG1_EXPIRED __BIT(29)
#define ISR_WDOG0_EXPIRED __BIT(28)
@@ -811,27 +809,27 @@
#define ISR_LAN_QUE2_FULL __BIT(16)
#define ISR_LAN_QUE1_FULL __BIT(15)
#define ISR_LAN_QUE0_FULL __BIT(14)
-#define FTC0_REL_THR 24
-#define FTC0_SET_THR 16
-#define FTC0_DROP_REL_THR 8
-#define FTC0_DROP_SET_THR 0
-#define FTC1_PER_PORT_THR 0
-#define PCTL0_WR_VAL(x) (((x) & 0xffff) << 16)
-#define PCTL0_RD_CMD __BIT(14)
-#define PCTL0_WR_CMD __BIT(13)
-#define PCTL0_REG(x) (((x) & 0x1f) << 8)
-#define PCTL0_ADDR(x) (((x) & 0x1f) << 0)
-#define PCTL1_RD_VAL(x) (((x) >> 16) & 0xffff)
-#define PCTL1_RD_DONE __BIT(1) /* read clear */
-#define PCTL1_WR_DONE __BIT(0) /* read clear */
-#define SGC2_WL_FC_EN __BIT(30)
+#define FTC0_REL_THR 24
+#define FTC0_SET_THR 16
+#define FTC0_DROP_REL_THR 8
+#define FTC0_DROP_SET_THR 0
+#define FTC1_PER_PORT_THR 0
+#define PCTL0_WR_VAL(x) (((x) & 0xffff) << 16)
+#define PCTL0_RD_CMD __BIT(14)
+#define PCTL0_WR_CMD __BIT(13)
+#define PCTL0_REG(x) (((x) & 0x1f) << 8)
+#define PCTL0_ADDR(x) (((x) & 0x1f) << 0)
+#define PCTL1_RD_VAL(x) (((x) >> 16) & 0xffff)
+#define PCTL1_RD_DONE __BIT(1) /* read clear */
+#define PCTL1_WR_DONE __BIT(0) /* read clear */
+#define SGC2_WL_FC_EN __BIT(30)
#define SGC2_PORT5_IS_LAN __BIT(29)
#define SGC2_PORT4_IS_LAN __BIT(28)
#define SGC2_PORT3_IS_LAN __BIT(27)
#define SGC2_PORT2_IS_LAN __BIT(26)
#define SGC2_PORT1_IS_LAN __BIT(25)
#define SGC2_PORT0_IS_LAN __BIT(24)
-#define SGC2_TX_CPU_TPID(x) ((x) << 16)
+#define SGC2_TX_CPU_TPID(x) ((x) << 16)
#define SGC2_ARBITER_LAN_EN __BIT(11)
#define SGC2_CPU_TPID_EN __BIT(10)
#define SGC2_DBL_TAG_EN5 __BIT(5)
@@ -842,306 +840,306 @@
#define SGC2_DBL_TAG_EN0 __BIT(0)
-#define FTC_THR_MSK 0xff
+#define FTC_THR_MSK 0xff
-#define PFC0_MTCC_LIMIT 24
-#define PFC0_TURN_OFF_CF 16
-#define PFC0_TURN_OFF_CF_MSK 0xff
-#define PFC0_VO_NUM 12
-#define PFC0_CL_NUM 8
-#define PFC0_BE_NUM 4
-#define PFC0_BK_NUM 0
-#define PFC0_NUM_MSK 0xf
+#define PFC0_MTCC_LIMIT 24
+#define PFC0_TURN_OFF_CF 16
+#define PFC0_TURN_OFF_CF_MSK 0xff
+#define PFC0_VO_NUM 12
+#define PFC0_CL_NUM 8
+#define PFC0_BE_NUM 4
+#define PFC0_BK_NUM 0
+#define PFC0_NUM_MSK 0xf
#define PFC1_P6_Q1_EN __BIT(31)
-#define PFC1_P6_TOS_EN __BIT(30)
-#define PFC1_P5_TOS_EN __BIT(29)
-#define PFC1_P4_TOS_EN __BIT(28)
-#define PFC1_P3_TOS_EN __BIT(27)
-
-#define PFC1_P1_TOS_EN __BIT(25)
-#define PFC1_P0_TOS_EN __BIT(24)
-#define PFC1_PORT_PRI6 12
-#define PFC1_PORT_PRI5 10
-#define PFC1_PORT_PRI4 8
-#define PFC1_PORT_PRI3 6
-#define PFC1_PORT_PRI2 4
-#define PFC1_PORT_PRI1 2
-#define PFC1_PORT_PRI0 0
-#define PFC1_PORT_MSK 0x3
-
-#define PFC2_PRI_THR_VO 24
-#define PFC2_PRI_THR_CL 16
-#define PFC2_PRI_THR_BE 8
-#define PFC2_PRI_THR_BK 0
-#define PFC2_PRI_THR_MSK 0xff
+#define PFC1_P6_TOS_EN __BIT(30)
+#define PFC1_P5_TOS_EN __BIT(29)
+#define PFC1_P4_TOS_EN __BIT(28)
+#define PFC1_P3_TOS_EN __BIT(27)
+
+#define PFC1_P1_TOS_EN __BIT(25)
+#define PFC1_P0_TOS_EN __BIT(24)
+#define PFC1_PORT_PRI6 12
+#define PFC1_PORT_PRI5 10
+#define PFC1_PORT_PRI4 8
+#define PFC1_PORT_PRI3 6
+#define PFC1_PORT_PRI2 4
+#define PFC1_PORT_PRI1 2
+#define PFC1_PORT_PRI0 0
+#define PFC1_PORT_MSK 0x3
+
+#define PFC2_PRI_THR_VO 24
+#define PFC2_PRI_THR_CL 16
+#define PFC2_PRI_THR_BE 8
+#define PFC2_PRI_THR_BK 0
+#define PFC2_PRI_THR_MSK 0xff
-#define GQC0_EMPTY_BLOCKS 0
-#define GQC0_EMPTY_BLOCKS_MSK 0xff
+#define GQC0_EMPTY_BLOCKS 0
+#define GQC0_EMPTY_BLOCKS_MSK 0xff
/*
* USB OTG Registers
*/
-#define RA_USB_OTG_OTG_CNTRL 0x000
-#define RA_USB_OTG_OTG_INT 0x004
-#define RA_USB_OTG_AHB_CFG 0x008
-#define RA_USB_OTG_CFG 0x00C
-#define RA_USB_OTG_RESET 0x010
-#define RA_USB_OTG_INT 0x014
-#define RA_USB_OTG_INT_MASK 0x018
-#define RA_USB_OTG_RX_STAT 0x01C
-#define RA_USB_OTG_RX_POP_STAT 0x020
-#define RA_USB_OTG_RX_FIFO_SZ 0x024
-#define RA_USB_OTG_TX_FIFO_SZ 0x028
-#define RA_USB_OTG_TX_FIFO_STAT 0x02C
-#define RA_USB_OTG_I2C_ACCESS 0x030
-#define RA_USB_OTG_PHY_CTL 0x034
-#define RA_USB_OTG_GPIO 0x038
-#define RA_USB_OTG_GUID 0x03C
-#define RA_USB_OTG_SNPSID 0x040
-#define RA_USB_OTG_HWCFG1 0x044
-#define RA_USB_OTG_HWCFG2 0x048
-#define RA_USB_OTG_HWCFG3 0x04C
-#define RA_USB_OTG_HWCFG4 0x050
-#define RA_USB_OTG_HC_TX_FIFO_SZ 0x100
-#define RA_USB_OTG_DV_TX_FIFO_SZ 0x104
-#define RA_USB_OTG_HC_CFG 0x400
-#define RA_USB_OTG_HC_FRM_INTRVL 0x404
-#define RA_USB_OTG_HC_FRM_NUM 0x408
-#define RA_USB_OTG_HC_TX_STAT 0x410
-#define RA_USB_OTG_HC_INT 0x414
-#define RA_USB_OTG_HC_INT_MASK 0x418
-#define RA_USB_OTG_HC_PORT 0x440
-#define RA_USB_OTG_HC_CH_CFG 0x500
-#define RA_USB_OTG_HC_CH_SPLT 0x504
-#define RA_USB_OTG_HC_CH_INT 0x508
-#define RA_USB_OTG_HC_CH_INT_MASK 0x50C
-#define RA_USB_OTG_HC_CH_XFER 0x510
-#define RA_USB_OTG_HC_CH_DMA_ADDR 0x514
-#define RA_USB_OTG_DV_CFG 0x800
-#define RA_USB_OTG_DV_CTL 0x804
-#define RA_USB_OTG_DV_STAT 0x808
-#define RA_USB_OTG_DV_IN_INT_MASK 0x810
-#define RA_USB_OTG_DV_OUT_INT_MASK 0x814
-#define RA_USB_OTG_DV_ALL_INT 0x818
-#define RA_USB_OTG_DV_EP_INT_MASK 0x81c
-#define RA_USB_OTG_DV_IN_SEQ_RQ1 0x820
-#define RA_USB_OTG_DV_IN_SEQ_RQ2 0x824
-#define RA_USB_OTG_DV_IN_SEQ_RQ3 0x830
-#define RA_USB_OTG_DV_IN_SEQ_RQ4 0x834
-#define RA_USB_OTG_DV_VBUS_DISCH 0x828
-#define RA_USB_OTG_DV_VBUS_PULSE 0x82c
-#define RA_USB_OTG_DV_THRESH_CTL 0x830
-#define RA_USB_OTG_DV_IN_FIFO_INT 0x834
-#define RA_USB_OTG_DV_IN0_CTL 0x900
-
-#define OTG_OTG_CNTRL_B_SESS_VALID __BIT(19)
-#define OTG_OTG_CNTRL_A_SESS_VALID __BIT(18)
-#define OTG_OTG_CNTRL_DEBOUNCE_SHORT __BIT(17)
-#define OTG_OTG_CNTRL_CONNID_STATUS __BIT(16)
+#define RA_USB_OTG_OTG_CNTRL 0x000
+#define RA_USB_OTG_OTG_INT 0x004
+#define RA_USB_OTG_AHB_CFG 0x008
+#define RA_USB_OTG_CFG 0x00C
+#define RA_USB_OTG_RESET 0x010
+#define RA_USB_OTG_INT 0x014
+#define RA_USB_OTG_INT_MASK 0x018
+#define RA_USB_OTG_RX_STAT 0x01C
+#define RA_USB_OTG_RX_POP_STAT 0x020
+#define RA_USB_OTG_RX_FIFO_SZ 0x024
+#define RA_USB_OTG_TX_FIFO_SZ 0x028
+#define RA_USB_OTG_TX_FIFO_STAT 0x02C
+#define RA_USB_OTG_I2C_ACCESS 0x030
+#define RA_USB_OTG_PHY_CTL 0x034
+#define RA_USB_OTG_GPIO 0x038
+#define RA_USB_OTG_GUID 0x03C
+#define RA_USB_OTG_SNPSID 0x040
+#define RA_USB_OTG_HWCFG1 0x044
+#define RA_USB_OTG_HWCFG2 0x048
+#define RA_USB_OTG_HWCFG3 0x04C
+#define RA_USB_OTG_HWCFG4 0x050
+#define RA_USB_OTG_HC_TX_FIFO_SZ 0x100
+#define RA_USB_OTG_DV_TX_FIFO_SZ 0x104
+#define RA_USB_OTG_HC_CFG 0x400
+#define RA_USB_OTG_HC_FRM_INTRVL 0x404
+#define RA_USB_OTG_HC_FRM_NUM 0x408
+#define RA_USB_OTG_HC_TX_STAT 0x410
+#define RA_USB_OTG_HC_INT 0x414
+#define RA_USB_OTG_HC_INT_MASK 0x418
+#define RA_USB_OTG_HC_PORT 0x440
+#define RA_USB_OTG_HC_CH_CFG 0x500
+#define RA_USB_OTG_HC_CH_SPLT 0x504
+#define RA_USB_OTG_HC_CH_INT 0x508
+#define RA_USB_OTG_HC_CH_INT_MASK 0x50C
+#define RA_USB_OTG_HC_CH_XFER 0x510
+#define RA_USB_OTG_HC_CH_DMA_ADDR 0x514
+#define RA_USB_OTG_DV_CFG 0x800
+#define RA_USB_OTG_DV_CTL 0x804
+#define RA_USB_OTG_DV_STAT 0x808
+#define RA_USB_OTG_DV_IN_INT_MASK 0x810
+#define RA_USB_OTG_DV_OUT_INT_MASK 0x814
+#define RA_USB_OTG_DV_ALL_INT 0x818
+#define RA_USB_OTG_DV_EP_INT_MASK 0x81c
+#define RA_USB_OTG_DV_IN_SEQ_RQ1 0x820
+#define RA_USB_OTG_DV_IN_SEQ_RQ2 0x824
+#define RA_USB_OTG_DV_IN_SEQ_RQ3 0x830
+#define RA_USB_OTG_DV_IN_SEQ_RQ4 0x834
+#define RA_USB_OTG_DV_VBUS_DISCH 0x828
+#define RA_USB_OTG_DV_VBUS_PULSE 0x82c
+#define RA_USB_OTG_DV_THRESH_CTL 0x830
+#define RA_USB_OTG_DV_IN_FIFO_INT 0x834
+#define RA_USB_OTG_DV_IN0_CTL 0x900
+
+#define OTG_OTG_CNTRL_B_SESS_VALID __BIT(19)
+#define OTG_OTG_CNTRL_A_SESS_VALID __BIT(18)
+#define OTG_OTG_CNTRL_DEBOUNCE_SHORT __BIT(17)
+#define OTG_OTG_CNTRL_CONNID_STATUS __BIT(16)
#define OTG_OTG_CNTRL_DV_HNP_EN __BIT(11)
-#define OTG_OTG_CNTRL_HC_SET_HNP_EN __BIT(10)
-#define OTG_OTG_CNTRL_HNP_REQ __BIT(9)
-#define OTG_OTG_CNTRL_HNP_SUCCESS __BIT(8)
-#define OTG_OTG_CNTRL_SESS_REQ __BIT(1)
-#define OTG_OTG_CNTRL_SESS_REQ_SUCCESS __BIT(0)
-#define OTG_OTG_INT_DEBOUNCE_DONE __BIT(19)
+#define OTG_OTG_CNTRL_HC_SET_HNP_EN __BIT(10)
+#define OTG_OTG_CNTRL_HNP_REQ __BIT(9)
+#define OTG_OTG_CNTRL_HNP_SUCCESS __BIT(8)
+#define OTG_OTG_CNTRL_SESS_REQ __BIT(1)
+#define OTG_OTG_CNTRL_SESS_REQ_SUCCESS __BIT(0)
+#define OTG_OTG_INT_DEBOUNCE_DONE __BIT(19)
#define OTG_OTG_INT_ADEV_TIMEOUT __BIT(18)
-#define OTG_OTG_INT_HOST_NEG_DETECT __BIT(17)
-#define OTG_OTG_INT_HOST_NEG_STATUS __BIT(9)
-#define OTG_OTG_INT_SESSION_REQ_STATUS __BIT(8)
-#define OTG_OTG_INT_SESSION_END_STATUS __BIT(2)
+#define OTG_OTG_INT_HOST_NEG_DETECT __BIT(17)
+#define OTG_OTG_INT_HOST_NEG_STATUS __BIT(9)
+#define OTG_OTG_INT_SESSION_REQ_STATUS __BIT(8)
+#define OTG_OTG_INT_SESSION_END_STATUS __BIT(2)
#define OTG_AHB_CFG_TX_PFIFO_EMPTY_INT_EN __BIT(8)
#define OTG_AHB_CFG_TX_NPFIFO_EMPTY_INT_EN __BIT(7)
#define OTG_AHB_CFG_DMA_EN __BIT(5)
-#define OTG_AHB_CFG_BURST(x) (((x) & 0xf) << 1)
-#define OTG_AHB_CFG_BURST_SINGLE 0
-#define OTG_AHB_CFG_BURST_INCR 1
-#define OTG_AHB_CFG_BURST_INCR4 3
-#define OTG_AHB_CFG_BURST_INCR8 5
-#define OTG_AHB_CFG_BURST_INCR16 7
+#define OTG_AHB_CFG_BURST(x) (((x) & 0xf) << 1)
+#define OTG_AHB_CFG_BURST_SINGLE 0
+#define OTG_AHB_CFG_BURST_INCR 1
+#define OTG_AHB_CFG_BURST_INCR4 3
+#define OTG_AHB_CFG_BURST_INCR8 5
+#define OTG_AHB_CFG_BURST_INCR16 7
#define OTG_AHB_CFG_GLOBAL_INT_EN __BIT(0)
-#define OTG_CFG_CORRUPT_TX __BIT(31)
-#define OTG_CFG_FORCE_DEVICE __BIT(30)
-#define OTG_CFG_FORCE_HOST __BIT(29)
-#define OTG_CFG_ULPI_EXT_VBUS_IND_SEL __BIT(22)
-#define OTG_CFG_ULPI_EXT_VBUS_IND __BIT(21)
-#define OTG_CFG_ULPI_EXT_VBUS_DRV __BIT(20)
-#define OTG_CFG_ULPI_CLOCK_SUSPEND __BIT(19)
+#define OTG_CFG_CORRUPT_TX __BIT(31)
+#define OTG_CFG_FORCE_DEVICE __BIT(30)
+#define OTG_CFG_FORCE_HOST __BIT(29)
+#define OTG_CFG_ULPI_EXT_VBUS_IND_SEL __BIT(22)
+#define OTG_CFG_ULPI_EXT_VBUS_IND __BIT(21)
+#define OTG_CFG_ULPI_EXT_VBUS_DRV __BIT(20)
+#define OTG_CFG_ULPI_CLOCK_SUSPEND __BIT(19)
#define OTG_CFG_ULPI_AUTO_RESUME __BIT(18)
-#define OTG_CFG_ULPI_FS_LS_SEL __BIT(17)
-#define OTG_CFG_UTMI_I2C_SEL __BIT(16)
-#define OTG_CFG_TURNAROUND_TIME(x) (((x) & 0xf) << 10)
+#define OTG_CFG_ULPI_FS_LS_SEL __BIT(17)
+#define OTG_CFG_UTMI_I2C_SEL __BIT(16)
+#define OTG_CFG_TURNAROUND_TIME(x) (((x) & 0xf) << 10)
#define OTG_CFG_HNP_CAP __BIT(9)
#define OTG_CFG_SRP_CAP __BIT(8)
-#define OTG_CFG_ULPI_DDR_SEL __BIT(7)
-#define OTG_CFG_HS_PHY_SEL __BIT(6)
-#define OTG_CFG_FS_IF_SEL __BIT(5)
-#define OTG_CFG_ULPI_UTMI_SEL __BIT(4)
-#define OTG_CFG_PHY_IF __BIT(3)
-#define OTG_CFG_TIMEOUT(x) (((x) & 0x7) << 0)
+#define OTG_CFG_ULPI_DDR_SEL __BIT(7)
+#define OTG_CFG_HS_PHY_SEL __BIT(6)
+#define OTG_CFG_FS_IF_SEL __BIT(5)
+#define OTG_CFG_ULPI_UTMI_SEL __BIT(4)
+#define OTG_CFG_PHY_IF __BIT(3)
+#define OTG_CFG_TIMEOUT(x) (((x) & 0x7) << 0)
#define OTG_RST_AHB_IDLE __BIT(31)
-#define OTG_RST_DMA_ACTIVE __BIT(30)
-#define OTG_RST_TXQ_TO_FLUSH(x) (((x) & 0x1f) << 6)
-#define OTG_RST_TXQ_FLUSH_ALL 0x10
-#define OTG_RST_TXQ_FLUSH __BIT(5)
-#define OTG_RST_RXQ_FLUSH __BIT(4)
-#define OTG_RST_INQ_FLUSH __BIT(3)
+#define OTG_RST_DMA_ACTIVE __BIT(30)
+#define OTG_RST_TXQ_TO_FLUSH(x) (((x) & 0x1f) << 6)
+#define OTG_RST_TXQ_FLUSH_ALL 0x10
+#define OTG_RST_TXQ_FLUSH __BIT(5)
+#define OTG_RST_RXQ_FLUSH __BIT(4)
+#define OTG_RST_INQ_FLUSH __BIT(3)
#define OTG_RST_HC_FRAME __BIT(2)
-#define OTG_RST_AHB __BIT(1)
-#define OTG_RST_CORE __BIT(0)
-#define OTG_INT_RESUME __BIT(31)
-#define OTG_INT_SESSION_REQ __BIT(30)
-#define OTG_INT_DISCONNECT __BIT(29)
-#define OTG_INT_CONNID_STATUS __BIT(28)
-#define OTG_INT_PTX_EMPTY __BIT(26)
-#define OTG_INT_HOST_CHANNEL __BIT(25)
-#define OTG_INT_PORT_STATUS __BIT(24)
-#define OTG_INT_DMA_FETCH_SUSPEND __BIT(22)
-#define OTG_INT_INCOMPLETE_PERIODIC __BIT(21)
+#define OTG_RST_AHB __BIT(1)
+#define OTG_RST_CORE __BIT(0)
+#define OTG_INT_RESUME __BIT(31)
+#define OTG_INT_SESSION_REQ __BIT(30)
+#define OTG_INT_DISCONNECT __BIT(29)
+#define OTG_INT_CONNID_STATUS __BIT(28)
+#define OTG_INT_PTX_EMPTY __BIT(26)
+#define OTG_INT_HOST_CHANNEL __BIT(25)
+#define OTG_INT_PORT_STATUS __BIT(24)
+#define OTG_INT_DMA_FETCH_SUSPEND __BIT(22)
+#define OTG_INT_INCOMPLETE_PERIODIC __BIT(21)
#define OTG_INT_INCOMPLETE_ISOC __BIT(20)
-#define OTG_INT_DV_OUT_EP __BIT(19)
+#define OTG_INT_DV_OUT_EP __BIT(19)
#define OTG_INT_DV_IN_EP __BIT(18)
-#define OTG_INT_DV_EP_MISMATCH __BIT(17)
+#define OTG_INT_DV_EP_MISMATCH __BIT(17)
#define OTG_INT_DV_PERIODIC_END __BIT(15)
#define OTG_INT_DV_ISOC_OUT_DROP __BIT(14)
#define OTG_INT_DV_ENUM_COMPLETE __BIT(13)
-#define OTG_INT_DV_USB_RESET __BIT(12)
-#define OTG_INT_DV_USB_SUSPEND __BIT(11)
-#define OTG_INT_DV_USB_EARLY_SUSPEND __BIT(10)
-#define OTG_INT_I2C __BIT(9)
-#define OTG_INT_ULPI_CARKIT __BIT(8)
-#define OTG_INT_DV_OUT_NAK_EFFECTIVE __BIT(7)
-#define OTG_INT_DV_IN_NAK_EFFECTIVE __BIT(6)
-#define OTG_INT_NPTX_EMPTY __BIT(5)
+#define OTG_INT_DV_USB_RESET __BIT(12)
+#define OTG_INT_DV_USB_SUSPEND __BIT(11)
+#define OTG_INT_DV_USB_EARLY_SUSPEND __BIT(10)
+#define OTG_INT_I2C __BIT(9)
+#define OTG_INT_ULPI_CARKIT __BIT(8)
+#define OTG_INT_DV_OUT_NAK_EFFECTIVE __BIT(7)
+#define OTG_INT_DV_IN_NAK_EFFECTIVE __BIT(6)
+#define OTG_INT_NPTX_EMPTY __BIT(5)
#define OTG_INT_RX_FIFO __BIT(4)
-#define OTG_INT_SOF __BIT(3)
-#define OTG_INT_OTG __BIT(2)
-#define OTG_INT_MODE_MISMATCH __BIT(1)
-#define OTG_INT_MODE __BIT(0)
-#define USB_OTG_SNPSID_CORE_REV_2_00 0x4F542000
-#define OTG_HC_CFG_FORCE_NO_HS __BIT(2)
-#define OTG_HC_CFG_FSLS_CLK_SEL(x) (((x) & 0x3) << 0)
-#define OTG_HC_CFG_FS_CLK_3060 0
-#define OTG_HC_CFG_FS_CLK_48 1
-#define OTG_HC_CFG_LS_CLK_3060 0
-#define OTG_HC_CFG_LS_CLK_48 1
-#define OTG_HC_CFG_LS_CLK_6 2
-#define USB_OTG_HC_FRM_NUM(x) (x & 0x3fff)
-#define USB_OTG_HC_FRM_REM(x) (x >> 16)
-#define USB_OTG_HC_PORT_SPEED(x) (((x) >> 17) & 0x3)
-#define USB_OTG_HC_PORT_SPEED_HS 0
-#define USB_OTG_HC_PORT_SPEED_FS 1
-#define USB_OTG_HC_PORT_SPEED_LS 2
-#define USB_OTG_HC_PORT_TEST(x) (((x) & 0xf) << 13)
-#define USB_OTG_HC_PORT_TEST_DISABLED 0
-#define USB_OTG_HC_PORT_TEST_J_MODE 1
-#define USB_OTG_HC_PORT_TEST_K_MODE 2
-#define USB_OTG_HC_PORT_TEST_NAK_MODE 3
-#define USB_OTG_HC_PORT_TEST_PKT_MODE 4
-#define USB_OTG_HC_PORT_TEST_FORCE_MODE 5
-#define USB_OTG_HC_PORT_POWER __BIT(12)
-#define USB_OTG_HC_PORT_LINE_STAT (((x) >> 10) & 0x3)
-#define USB_OTG_HC_PORT_LINE_STAT_DP 1
-#define USB_OTG_HC_PORT_LINE_STAT_DM 3
-#define USB_OTG_HC_PORT_RESET __BIT(8)
+#define OTG_INT_SOF __BIT(3)
+#define OTG_INT_OTG __BIT(2)
+#define OTG_INT_MODE_MISMATCH __BIT(1)
+#define OTG_INT_MODE __BIT(0)
+#define USB_OTG_SNPSID_CORE_REV_2_00 0x4F542000
+#define OTG_HC_CFG_FORCE_NO_HS __BIT(2)
+#define OTG_HC_CFG_FSLS_CLK_SEL(x) (((x) & 0x3) << 0)
+#define OTG_HC_CFG_FS_CLK_3060 0
+#define OTG_HC_CFG_FS_CLK_48 1
+#define OTG_HC_CFG_LS_CLK_3060 0
+#define OTG_HC_CFG_LS_CLK_48 1
+#define OTG_HC_CFG_LS_CLK_6 2
+#define USB_OTG_HC_FRM_NUM(x) (x & 0x3fff)
+#define USB_OTG_HC_FRM_REM(x) (x >> 16)
+#define USB_OTG_HC_PORT_SPEED(x) (((x) >> 17) & 0x3)
+#define USB_OTG_HC_PORT_SPEED_HS 0
+#define USB_OTG_HC_PORT_SPEED_FS 1
+#define USB_OTG_HC_PORT_SPEED_LS 2
+#define USB_OTG_HC_PORT_TEST(x) (((x) & 0xf) << 13)
+#define USB_OTG_HC_PORT_TEST_DISABLED 0
+#define USB_OTG_HC_PORT_TEST_J_MODE 1
+#define USB_OTG_HC_PORT_TEST_K_MODE 2
+#define USB_OTG_HC_PORT_TEST_NAK_MODE 3
+#define USB_OTG_HC_PORT_TEST_PKT_MODE 4
+#define USB_OTG_HC_PORT_TEST_FORCE_MODE 5
+#define USB_OTG_HC_PORT_POWER __BIT(12)
+#define USB_OTG_HC_PORT_LINE_STAT (((x) >> 10) & 0x3)
+#define USB_OTG_HC_PORT_LINE_STAT_DP 1
+#define USB_OTG_HC_PORT_LINE_STAT_DM 3
+#define USB_OTG_HC_PORT_RESET __BIT(8)
#define USB_OTG_HC_PORT_SUSPEND __BIT(7)
-#define USB_OTG_HC_PORT_RESUME __BIT(6)
-#define USB_OTG_HC_PORT_OVCURR_CHANGE __BIT(5)
-#define USB_OTG_HC_PORT_OVCURR __BIT(4)
-#define USB_OTG_HC_PORT_ENABLE_CHANGE __BIT(3)
-#define USB_OTG_HC_PORT_ENABLE __BIT(2)
-#define USB_OTG_HC_PORT_CONNECT_CHANGE __BIT(1)
-#define USB_OTG_HC_PORT_STATUS __BIT(0)
+#define USB_OTG_HC_PORT_RESUME __BIT(6)
+#define USB_OTG_HC_PORT_OVCURR_CHANGE __BIT(5)
+#define USB_OTG_HC_PORT_OVCURR __BIT(4)
+#define USB_OTG_HC_PORT_ENABLE_CHANGE __BIT(3)
+#define USB_OTG_HC_PORT_ENABLE __BIT(2)
+#define USB_OTG_HC_PORT_CONNECT_CHANGE __BIT(1)
+#define USB_OTG_HC_PORT_STATUS __BIT(0)
#define USB_OTG_HC_CH_CFG_ENABLE __BIT(31)
#define USB_OTG_HC_CH_CFG_DISABLE __BIT(30)
-#define USB_OTG_HC_CH_CFG_ODD_FRAME __BIT(29)
-#define USB_OTG_HC_CH_CFG_DEV_ADDR(x) (((x) & 0x7f) << 22)
-#define USB_OTG_HC_CH_CFG_MULTI_CNT(x) (((x) & 0x3) << 20)
-#define USB_OTG_HC_CH_CFG_EP_TYPE(x) (((x) & 0x3) << 18)
-#define USB_OTG_HC_CH_CFG_EP_TYPE_CTRL 0
-#define USB_OTG_HC_CH_CFG_EP_TYPE_ISOC 1
-#define USB_OTG_HC_CH_CFG_EP_TYPE_BULK 2
-#define USB_OTG_HC_CH_CFG_EP_TYPE_INTR 3
-#define USB_OTG_HC_CH_CFG_LS __BIT(17)
-#define USB_OTG_HC_CH_CFG_EP_DIR(x) (((x) & 0x1) << 15)
-#define USB_OTG_HC_CH_CFG_EP_DIR_OUT 0
-#define USB_OTG_HC_CH_CFG_EP_DIR_IN 1
-#define USB_OTG_HC_CH_CFG_EP_NUM(x) (((x) & 0xf) << 11)
-#define USB_OTG_HC_CH_CFG_MAX_PKT_SZ(x) (((x) & 0x7ff) << 0)
-#define USB_OTG_HC_CH_SPLT_EN __BIT(31)
-#define USB_OTG_HC_CH_SPLT_COMPLETE __BIT(16)
-#define USB_OTG_HC_CH_SPLT_POS(x) (((x) & 0x3) << 14)
-#define USB_OTG_HC_CH_SPLT_POS_MID 0
-#define USB_OTG_HC_CH_SPLT_POS_END 1
-#define USB_OTG_HC_CH_SPLT_POS_BEGIN 2
-#define USB_OTG_HC_CH_SPLT_POS_ALL 3
-#define USB_OTG_HC_CH_SPLT_HUB_ADDR(x) (((x) & 0x7f) << 7)
-#define USB_OTG_HC_CH_SPLT_PORT_ADDR(x) (((x) & 0x7f) << 0)
-#define USB_OTG_HC_CH_INT_ALL 0x7ff
-#define USB_OTG_HC_CH_INT_TOGGLE_ERROR __BIT(10)
+#define USB_OTG_HC_CH_CFG_ODD_FRAME __BIT(29)
+#define USB_OTG_HC_CH_CFG_DEV_ADDR(x) (((x) & 0x7f) << 22)
+#define USB_OTG_HC_CH_CFG_MULTI_CNT(x) (((x) & 0x3) << 20)
+#define USB_OTG_HC_CH_CFG_EP_TYPE(x) (((x) & 0x3) << 18)
+#define USB_OTG_HC_CH_CFG_EP_TYPE_CTRL 0
+#define USB_OTG_HC_CH_CFG_EP_TYPE_ISOC 1
+#define USB_OTG_HC_CH_CFG_EP_TYPE_BULK 2
+#define USB_OTG_HC_CH_CFG_EP_TYPE_INTR 3
+#define USB_OTG_HC_CH_CFG_LS __BIT(17)
+#define USB_OTG_HC_CH_CFG_EP_DIR(x) (((x) & 0x1) << 15)
+#define USB_OTG_HC_CH_CFG_EP_DIR_OUT 0
+#define USB_OTG_HC_CH_CFG_EP_DIR_IN 1
+#define USB_OTG_HC_CH_CFG_EP_NUM(x) (((x) & 0xf) << 11)
+#define USB_OTG_HC_CH_CFG_MAX_PKT_SZ(x) (((x) & 0x7ff) << 0)
+#define USB_OTG_HC_CH_SPLT_EN __BIT(31)
+#define USB_OTG_HC_CH_SPLT_COMPLETE __BIT(16)
+#define USB_OTG_HC_CH_SPLT_POS(x) (((x) & 0x3) << 14)
+#define USB_OTG_HC_CH_SPLT_POS_MID 0
+#define USB_OTG_HC_CH_SPLT_POS_END 1
+#define USB_OTG_HC_CH_SPLT_POS_BEGIN 2
+#define USB_OTG_HC_CH_SPLT_POS_ALL 3
+#define USB_OTG_HC_CH_SPLT_HUB_ADDR(x) (((x) & 0x7f) << 7)
+#define USB_OTG_HC_CH_SPLT_PORT_ADDR(x) (((x) & 0x7f) << 0)
+#define USB_OTG_HC_CH_INT_ALL 0x7ff
+#define USB_OTG_HC_CH_INT_TOGGLE_ERROR __BIT(10)
#define USB_OTG_HC_CH_INT_FRAME_OVERRUN __BIT(9)
-#define USB_OTG_HC_CH_INT_BABBLE_ERROR __BIT(8)
-#define USB_OTG_HC_CH_INT_XACT_ERROR __BIT(7)
-#define USB_OTG_HC_CH_INT_NYET __BIT(6)
-#define USB_OTG_HC_CH_INT_ACK __BIT(5)
-#define USB_OTG_HC_CH_INT_NAK __BIT(4)
+#define USB_OTG_HC_CH_INT_BABBLE_ERROR __BIT(8)
+#define USB_OTG_HC_CH_INT_XACT_ERROR __BIT(7)
+#define USB_OTG_HC_CH_INT_NYET __BIT(6)
+#define USB_OTG_HC_CH_INT_ACK __BIT(5)
+#define USB_OTG_HC_CH_INT_NAK __BIT(4)
#define USB_OTG_HC_CH_INT_STALL __BIT(3)
-#define USB_OTG_HC_CH_INT_DMA_ERROR __BIT(2)
+#define USB_OTG_HC_CH_INT_DMA_ERROR __BIT(2)
#define USB_OTG_HC_CH_INT_HALTED __BIT(1)
#define USB_OTG_HC_CH_INT_XFER_COMPLETE __BIT(0)
-#define USB_OTG_HC_CH_XFER_DO_PING __BIT(31)
-#define USB_OTG_HC_CH_WR_XFER_PID(x) (((x) & 0x3) << 29)
-#define USB_OTG_HC_CH_RD_XFER_PID(x) (((x) >> 29) & 0x3)
-#define USB_OTG_HC_CH_XFER_PID_DATA0 0
-#define USB_OTG_HC_CH_XFER_PID_DATA2 1
-#define USB_OTG_HC_CH_XFER_PID_DATA1 2
-#define USB_OTG_HC_CH_XFER_PID_SETUP 3
-#define USB_OTG_HC_CH_XFER_PID_MDATA 3
-#define USB_OTG_HC_CH_XFER_SET_PKT_CNT(x) (((x) & 0x3ff) << 19)
-#define USB_OTG_HC_CH_XFER_SET_BYTES(x) ((x) & 0x7ffff)
-#define USB_OTG_HC_CH_XFER_GET_PKT_CNT(x) (((x) >> 19) & 0x3ff)
-#define USB_OTG_HC_CH_XFER_GET_BYTES(x) ((x) & 0x7ffff)
+#define USB_OTG_HC_CH_XFER_DO_PING __BIT(31)
+#define USB_OTG_HC_CH_WR_XFER_PID(x) (((x) & 0x3) << 29)
+#define USB_OTG_HC_CH_RD_XFER_PID(x) (((x) >> 29) & 0x3)
+#define USB_OTG_HC_CH_XFER_PID_DATA0 0
+#define USB_OTG_HC_CH_XFER_PID_DATA2 1
+#define USB_OTG_HC_CH_XFER_PID_DATA1 2
+#define USB_OTG_HC_CH_XFER_PID_SETUP 3
+#define USB_OTG_HC_CH_XFER_PID_MDATA 3
+#define USB_OTG_HC_CH_XFER_SET_PKT_CNT(x) (((x) & 0x3ff) << 19)
+#define USB_OTG_HC_CH_XFER_SET_BYTES(x) ((x) & 0x7ffff)
+#define USB_OTG_HC_CH_XFER_GET_PKT_CNT(x) (((x) >> 19) & 0x3ff)
+#define USB_OTG_HC_CH_XFER_GET_BYTES(x) ((x) & 0x7ffff)
/* PCIe Registers - 0x10140000 */
-#define RA_PCI_PCICFG 0x0000
-#define PCICFG_P2P_BR_DEVNUM1 __BITS(23,20)
-#define PCICFG_P2P_BR_DEVNUM0 __BITS(19,16)
-#define PCICFG_PSIRST __BIT(1)
-#define RA_PCI_PCIINT 0x0008
-#define PCIINT_INT3 __BIT(21) // PCIe1 interrupt
-#define PCIINT_INT2 __BIT(20) // PCIe0 interrupt
-#define PCIINT_INT1 __BIT(19)
-#define PCIINT_INT0 __BIT(18)
-#define RA_PCI_PCIENA 0x000c
-#define RA_PCI_CFGADDR 0x0020
-#define CFGADDR_EXTREG __BITS(27,24)
-#define CFGADDR_BUS __BITS(23,16)
-#define CFGADDR_DEV __BITS(15,11)
-#define CFGADDR_FUN __BITS(10,8)
-#define CFGADDR_REG __BITS(7,0)
-#define RA_PCI_CFGDATA 0x0024
-#define RA_PCI_MEMBASE 0x0028
-#define MEMBASE_ADDR __BITS(31,16)
-#define RA_PCI_IOBASE 0x002c
-#define IOBASE_ADDR __BITS(31,16)
-#define RA_PCI_PHY0CFG 0x0090
-#define PHY0CFG_SPI_BUSY __BIT(31)
-#define PHY0CFG_SPI_WR __BIT(23)
-#define PHY0CFG_SPI_ADDR __BITS(15,8)
-#define PHY0CFG_SPI_DATA __BITS(7,0)
+#define RA_PCI_PCICFG 0x0000
+#define PCICFG_P2P_BR_DEVNUM1 __BITS(23,20)
+#define PCICFG_P2P_BR_DEVNUM0 __BITS(19,16)
+#define PCICFG_PSIRST __BIT(1)
+#define RA_PCI_PCIINT 0x0008
+#define PCIINT_INT3 __BIT(21) // PCIe1 interrupt
+#define PCIINT_INT2 __BIT(20) // PCIe0 interrupt
+#define PCIINT_INT1 __BIT(19)
+#define PCIINT_INT0 __BIT(18)
+#define RA_PCI_PCIENA 0x000c
+#define RA_PCI_CFGADDR 0x0020
+#define CFGADDR_EXTREG __BITS(27,24)
+#define CFGADDR_BUS __BITS(23,16)
+#define CFGADDR_DEV __BITS(15,11)
+#define CFGADDR_FUN __BITS(10,8)
+#define CFGADDR_REG __BITS(7,0)
+#define RA_PCI_CFGDATA 0x0024
+#define RA_PCI_MEMBASE 0x0028
+#define MEMBASE_ADDR __BITS(31,16)
+#define RA_PCI_IOBASE 0x002c
+#define IOBASE_ADDR __BITS(31,16)
+#define RA_PCI_PHY0CFG 0x0090
+#define PHY0CFG_SPI_BUSY __BIT(31)
+#define PHY0CFG_SPI_WR __BIT(23)
+#define PHY0CFG_SPI_ADDR __BITS(15,8)
+#define PHY0CFG_SPI_DATA __BITS(7,0)
/* PCIe0 RC Control Registers - 0x10142000 */
-#define RA_PCIE0_BAR0SETUP 0x0010
-#define BARSETUP_BARMSK __BITS(31,16)
-#define BARSETUP_BARENB __BIT(0)
-#define RA_PCIE0_BAR1SETUP 0x0014
-#define RA_PCIE0_IMBASEBAR0 0x0018
-#define IMBASEBAR0 __BITS(31,16)
-#define RA_PCIE0_ID 0x0010
-#define RA_PCIE0_CLASS 0x0014
-#define RA_PCIE0_SUBID 0x0018
-#define RA_PCIE0_STATUS 0x0018
-#define PCIE_STATUS_LINK_UP __BIT(0)
+#define RA_PCIE0_BAR0SETUP 0x0010
+#define BARSETUP_BARMSK __BITS(31,16)
+#define BARSETUP_BARENB __BIT(0)
+#define RA_PCIE0_BAR1SETUP 0x0014
+#define RA_PCIE0_IMBASEBAR0 0x0018
+#define IMBASEBAR0 __BITS(31,16)
+#define RA_PCIE0_ID 0x0010
+#define RA_PCIE0_CLASS 0x0014
+#define RA_PCIE0_SUBID 0x0018
+#define RA_PCIE0_STATUS 0x0018
+#define PCIE_STATUS_LINK_UP __BIT(0)
#endif /* _RALINK_REG_H_ */
