Module Name: src
Committed By: ryo
Date: Wed Oct 5 15:54:58 UTC 2016
Modified Files:
src/sys/arch/evbmips/conf: files.rasoc
src/sys/arch/evbmips/rasoc: autoconf.c console.c machdep.c
src/sys/arch/mips/ralink: ralink_com.c ralink_eth.c ralink_gpio.c
ralink_gpio.h ralink_intr.c ralink_mainbus.c ralink_reg.h
ralink_var.h
Added Files:
src/sys/arch/evbmips/conf: LINKITSMART7688
Log Message:
add support MT7628/MediaTek LinkIt Smart 7688
by @hiroshi and me.
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbmips/conf/LINKITSMART7688
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/evbmips/conf/files.rasoc
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbmips/rasoc/autoconf.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/evbmips/rasoc/console.c
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/evbmips/rasoc/machdep.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/ralink/ralink_com.c \
src/sys/arch/mips/ralink/ralink_intr.c \
src/sys/arch/mips/ralink/ralink_mainbus.c
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/mips/ralink/ralink_eth.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/mips/ralink/ralink_gpio.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/ralink/ralink_gpio.h
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/mips/ralink/ralink_reg.h
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/mips/ralink/ralink_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbmips/conf/files.rasoc
diff -u src/sys/arch/evbmips/conf/files.rasoc:1.4 src/sys/arch/evbmips/conf/files.rasoc:1.5
--- src/sys/arch/evbmips/conf/files.rasoc:1.4 Sun Jul 20 10:22:54 2014
+++ src/sys/arch/evbmips/conf/files.rasoc Wed Oct 5 15:54:58 2016
@@ -1,6 +1,6 @@
-# $NetBSD: files.rasoc,v 1.4 2014/07/20 10:22:54 alnsn Exp $
+# $NetBSD: files.rasoc,v 1.5 2016/10/05 15:54:58 ryo Exp $
-defflag opt_rasoc.h RT3050 RT3052 RT3883 MT7620
+defflag opt_rasoc.h RT3050 RT3052 RT3883 MT7620 MT7628
file arch/mips/mips/bus_dma.c
file arch/mips/mips/mips3_clock.c
@@ -15,7 +15,7 @@ file arch/evbmips/rasoc/machdep.c
file arch/evbmips/rasoc/console.c
# System bus
-device mainbus { }
+device mainbus { [addr = -1] }
attach mainbus at root
file arch/mips/ralink/ralink_mainbus.c mainbus
@@ -41,6 +41,9 @@ include "dev/scsipi/files.scsipi"
# Machine-independent USB device support
include "dev/usb/files.usb"
+# Machine-independent Bluetooth device support
+include "dev/bluetooth/files.bluetooth"
+
# Memory Disk
file dev/md_root.c memory_disk_hooks
Index: src/sys/arch/evbmips/rasoc/autoconf.c
diff -u src/sys/arch/evbmips/rasoc/autoconf.c:1.5 src/sys/arch/evbmips/rasoc/autoconf.c:1.6
--- src/sys/arch/evbmips/rasoc/autoconf.c:1.5 Wed Apr 30 01:02:40 2014
+++ src/sys/arch/evbmips/rasoc/autoconf.c Wed Oct 5 15:54:58 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: autoconf.c,v 1.5 2014/04/30 01:02:40 matt Exp $ */
+/* $NetBSD: autoconf.c,v 1.6 2016/10/05 15:54:58 ryo Exp $ */
/*-
* Copyright (c) 2011 CradlePoint Technology, Inc.
* All rights reserved.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.5 2014/04/30 01:02:40 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.6 2016/10/05 15:54:58 ryo Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -69,6 +69,15 @@ static const struct cfg_info {
uint32_t map_rst;
uint32_t map_clkcfg1;
} map_info[] = {
+#if defined(MT7628)
+ { "rpci", RST_PCIE0_7620, SYSCTL_CLKCFG1_PCIE_CLK_EN_7620 },
+ { "ohci", RST_UHST0_7620|RST_UHST,
+ SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620|SYSCTL_CLKCFG1_UPHY0_CLK_EN_7628 },
+ { "ehci", RST_UHST0_7620|RST_UHST,
+ SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620|SYSCTL_CLKCFG1_UPHY0_CLK_EN_7628 },
+ { "sdhc", RST_SDHC_7620, SYSCTL_CLKCFG1_SDHC_CLK_EN },
+ { "rsw", RST_ESW_7620, SYSCTL_CLKCFG1_ESW_CLK_EN },
+#endif
#if defined(MT7620)
{ "rpci", RST_PCIE0_7620, SYSCTL_CLKCFG1_PCIE_CLK_EN_7620 },
{ "ohci", RST_UHST0_7620|RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620 },
Index: src/sys/arch/evbmips/rasoc/console.c
diff -u src/sys/arch/evbmips/rasoc/console.c:1.2 src/sys/arch/evbmips/rasoc/console.c:1.3
--- src/sys/arch/evbmips/rasoc/console.c:1.2 Thu Jul 28 15:50:13 2011
+++ src/sys/arch/evbmips/rasoc/console.c Wed Oct 5 15:54:58 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: console.c,v 1.2 2011/07/28 15:50:13 matt Exp $ */
+/* $NetBSD: console.c,v 1.3 2016/10/05 15:54:58 ryo Exp $ */
/*-
* Copyright (c) 2011 CradlePoint Technology, Inc.
* All rights reserved.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: console.c,v 1.2 2011/07/28 15:50:13 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: console.c,v 1.3 2016/10/05 15:54:58 ryo Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -38,6 +38,9 @@ __KERNEL_RCSID(0, "$NetBSD: console.c,v
#include <mips/ralink/ralink_reg.h>
#include <mips/ralink/ralink_var.h>
+#ifndef RALINK_CONADDR
+#define RALINK_CONADDR RA_UART_LITE_BASE /* default console is UART_LITE */
+#endif
static inline uint32_t
sysctl_read(const u_int offset)
@@ -54,13 +57,13 @@ sysctl_write(const u_int offset, uint32_
static inline uint32_t
uart_read(const u_int offset)
{
- return *RA_IOREG_VADDR(RA_UART_LITE_BASE, offset);
+ return *RA_IOREG_VADDR(RALINK_CONADDR, offset);
}
static inline void
uart_write(const u_int offset, const uint32_t val)
{
- *RA_IOREG_VADDR(RA_UART_LITE_BASE, offset) = val;
+ *RA_IOREG_VADDR(RALINK_CONADDR, offset) = val;
}
#ifdef RA_CONSOLE_EARLY
Index: src/sys/arch/evbmips/rasoc/machdep.c
diff -u src/sys/arch/evbmips/rasoc/machdep.c:1.11 src/sys/arch/evbmips/rasoc/machdep.c:1.12
--- src/sys/arch/evbmips/rasoc/machdep.c:1.11 Fri Jun 26 22:14:01 2015
+++ src/sys/arch/evbmips/rasoc/machdep.c Wed Oct 5 15:54:58 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.11 2015/06/26 22:14:01 matt Exp $ */
+/* $NetBSD: machdep.c,v 1.12 2016/10/05 15:54:58 ryo Exp $ */
/*-
* Copyright (c) 2011 CradlePoint Technology, Inc.
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.11 2015/06/26 22:14:01 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.12 2016/10/05 15:54:58 ryo Exp $");
#include <sys/param.h>
#include <sys/boot_flag.h>
@@ -162,7 +162,7 @@ mach_init(void)
/*
* Determine the memory size.
*/
-#if defined(MT7620)
+#if defined(MT7620) || defined(MT7628)
memsize = 128 << 20;
#else
memsize = *(volatile uint32_t *)
Index: src/sys/arch/mips/ralink/ralink_com.c
diff -u src/sys/arch/mips/ralink/ralink_com.c:1.4 src/sys/arch/mips/ralink/ralink_com.c:1.5
--- src/sys/arch/mips/ralink/ralink_com.c:1.4 Wed Apr 30 00:51:26 2014
+++ src/sys/arch/mips/ralink/ralink_com.c Wed Oct 5 15:54:58 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: ralink_com.c,v 1.4 2014/04/30 00:51:26 matt Exp $ */
+/* $NetBSD: ralink_com.c,v 1.5 2016/10/05 15:54:58 ryo Exp $ */
/*-
* Copyright (c) 2011 CradlePoint Technology, Inc.
* All rights reserved.
@@ -130,8 +130,9 @@
/* ralink_com.c -- Ralink 3052 uart console driver */
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ralink_com.c,v 1.4 2014/04/30 00:51:26 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ralink_com.c,v 1.5 2016/10/05 15:54:58 ryo Exp $");
+#include "locators.h"
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
@@ -153,8 +154,10 @@ __KERNEL_RCSID(0, "$NetBSD: ralink_com.c
#include "opt_com.h"
struct ralink_com_softc {
- struct com_softc sc_com;
- void * sc_ih;
+ struct com_softc sc_com;
+ void *sc_ih;
+ bus_addr_t sc_addr;
+ int sc_irq;
};
static int ralink_com_match(device_t, cfdata_t , void *);
@@ -171,6 +174,57 @@ CFATTACH_DECL_NEW(ralink_com, sizeof(str
#error COM_REGMAP not defined!
#endif
+#ifndef RALINK_CONADDR
+#define RALINK_CONADDR RA_UART_LITE_BASE /* default console is UART_LITE */
+#endif
+
+/* address/irq/rst/gpiomode mappings */
+static struct {
+ bus_addr_t addr;
+ int irq;
+ uint32_t rst;
+ uint32_t gpiomode;
+} ralink_uart_maps[] = {
+#ifdef MT7628
+ { RA_UART_LITE_BASE, RA_IRQ_UARTL, RST_UART0_7628, GPIO1MODE_UART0 },
+ { RA_UART1_BASE, RA_IRQ_UART1, RST_UART1_7628, GPIO1MODE_UART1 },
+ { RA_UART2_BASE, RA_IRQ_UART2, RST_UART2_7628, GPIO1MODE_UART2 },
+#else
+ { RA_UART_BASE, RA_IRQ_UARTF, RST_UART, GPIOMODE_UARTF0 },
+ { RA_UART_LITE_BASE, RA_IRQ_UARTL, RST_UARTL, GPIOMODE_UARTL }
+#endif
+};
+
+static inline int
+ra_uart2irq(bus_addr_t addr)
+{
+ int i;
+ for (i = 0; __arraycount(ralink_uart_maps); i++)
+ if (ralink_uart_maps[i].addr == addr)
+ return ralink_uart_maps[i].irq;
+ return -1;
+}
+
+static inline uint32_t
+ra_uart2rst(bus_addr_t addr)
+{
+ int i;
+ for (i = 0; __arraycount(ralink_uart_maps); i++)
+ if (ralink_uart_maps[i].addr == addr)
+ return ralink_uart_maps[i].rst;
+ return 0;
+}
+
+static inline uint32_t
+ra_uart2gpiomode(bus_addr_t addr)
+{
+ int i;
+ for (i = 0; __arraycount(ralink_uart_maps); i++)
+ if (ralink_uart_maps[i].addr == addr)
+ return ralink_uart_maps[i].gpiomode;
+ return 0;
+}
+
static inline uint32_t
sysctl_read(const u_int offset)
{
@@ -186,20 +240,20 @@ sysctl_write(const u_int offset, uint32_
static inline uint32_t
uart_read(const u_int offset)
{
- return *RA_IOREG_VADDR(RA_UART_LITE_BASE, offset);
+ return *RA_IOREG_VADDR(RALINK_CONADDR, offset);
}
static inline void
uart_write(const u_int offset, const uint32_t val)
{
- *RA_IOREG_VADDR(RA_UART_LITE_BASE, offset) = val;
+ *RA_IOREG_VADDR(RALINK_CONADDR, offset) = val;
}
#ifdef RALINK_CONSOLE_EARLY
static int
ralink_cngetc(dev_t dv)
{
- if ((uart_read(RA_UART_LSR) & LSR_RXRDY) == 0)
+ if ((uart_read(RA_UART_LSR) & LSR_RXRDY) == 0)
return -1;
return uart_read(RA_UART_RBR) & 0xff;
@@ -210,14 +264,14 @@ ralink_cnputc(dev_t dv, int c)
{
int timo = 150000;
- while ((uart_read(RA_UART_LSR) & LSR_TXRDY) == 0 && --timo > 0)
+ while ((uart_read(RA_UART_LSR) & LSR_TXRDY) == 0 && --timo > 0)
;
uart_write(RA_UART_TBR, c);
__asm __volatile("sync");
timo = 150000;
- while ((uart_read(RA_UART_LSR) & LSR_TSRE) == 0 && --timo > 0)
+ while ((uart_read(RA_UART_LSR) & LSR_TSRE) == 0 && --timo > 0)
;
}
@@ -238,15 +292,26 @@ ralink_console_early(void)
int
ralink_com_match(device_t parent, cfdata_t cf, void *aux)
{
+ const struct mainbus_attach_args *ma;
+ bus_addr_t addr;
+
+ ma = aux;
+ addr = ma->ma_addr;
+ if (addr == MAINBUSCF_ADDR_DEFAULT)
+ addr = RA_UART_LITE_BASE;
+
+ if (ra_uart2irq(addr) < 0)
+ return 0;
+
if (cn_tab == NULL || cn_tab->cn_pri < CN_NORMAL) {
printf("NULL console set, don't install ourselves "
- "(of course this shouldn't print)");
+ "(of course this shouldn't print)");
return 0;
}
/*
* If we got this far, assume we want to install it as the console.
- * No need to probe. Future possibilities include checking to see if it
+ * No need to probe. Future possibilities include checking to see if it
* is console or KGDB but now it is our only console method if we aren't
* forcing a null console
*/
@@ -262,23 +327,50 @@ ralink_com_attach(device_t parent, devic
bus_space_handle_t ioh;
int error;
- if ((error = bus_space_map(ma->ma_memt, RA_UART_LITE_BASE,
- 0x1000, 0, &ioh)) != 0) {
+ /* opt addr and irq */
+ rtsc->sc_addr = ma->ma_addr;
+ if (rtsc->sc_addr == MAINBUSCF_ADDR_DEFAULT)
+ rtsc->sc_addr = RA_UART_LITE_BASE;
+ rtsc->sc_irq = ra_uart2irq(rtsc->sc_addr);
+
+ if ((error = bus_space_map(ma->ma_memt, rtsc->sc_addr,
+ RA_UART_SIZE, 0, &ioh)) != 0) {
aprint_error(": can't map registers, error=%d\n", error);
return;
}
- COM_INIT_REGS(sc->sc_regs, ma->ma_memt, ioh, RA_UART_LITE_BASE);
sc->sc_dev = self;
sc->sc_frequency = RA_UART_FREQ;
- sc->sc_regs.cr_nports = 0x1000;
+ sc->sc_regs.cr_nports = 32;
+#if defined(MT7628)
+ sc->sc_type = COM_TYPE_NORMAL;
+#else
sc->sc_type = COM_TYPE_AU1x00;
+#endif
sc->enabled = 1;
- ralink_com_initmap(&sc->sc_regs);
+ /* reset hardware if not a console */
+ if (rtsc->sc_addr != RALINK_CONADDR) {
+ uint32_t r;
+
+ /* reset */
+ r = sysctl_read(RA_SYSCTL_RST);
+ r |= ra_uart2rst(rtsc->sc_addr);
+ sysctl_write(RA_SYSCTL_RST, r);
+ r ^= ra_uart2rst(rtsc->sc_addr);
+ sysctl_write(RA_SYSCTL_RST, r);
- rtsc->sc_ih = ra_intr_establish(RA_IRQ_UARTL, comintr, sc, 1);
+ /* make sure we are in UART mode */
+ r = sysctl_read(RA_SYSCTL_GPIOMODE);
+ r &= ra_uart2gpiomode(rtsc->sc_addr);
+ r |= __SHIFTIN(0, ra_uart2gpiomode(rtsc->sc_addr));
+ sysctl_write(RA_SYSCTL_GPIOMODE, r);
+ }
+
+ COM_INIT_REGS(sc->sc_regs, ma->ma_memt, ioh, rtsc->sc_addr);
+ ralink_com_initmap(&sc->sc_regs);
+ rtsc->sc_ih = ra_intr_establish(rtsc->sc_irq, comintr, sc, 1);
com_attach_subr(sc);
}
@@ -288,6 +380,9 @@ ralink_com_initmap(struct com_regs *regs
regsp->cr_map[COM_REG_RXDATA] = RA_UART_RBR;
regsp->cr_map[COM_REG_TXDATA] = RA_UART_TBR;
regsp->cr_map[COM_REG_DLBL] = RA_UART_DLL;
+#if defined(MT7628)
+ regsp->cr_map[COM_REG_DLBH] = RA_UART_DLM;
+#endif
regsp->cr_map[COM_REG_IER] = RA_UART_IER;
regsp->cr_map[COM_REG_IIR] = RA_UART_IIR;
regsp->cr_map[COM_REG_FIFO] = RA_UART_FCR;
@@ -298,7 +393,7 @@ ralink_com_initmap(struct com_regs *regs
}
void
-ralink_com_early(int silent)
+ralink_com_early(int silent)
{
struct com_regs regs;
uint32_t r;
@@ -306,9 +401,9 @@ ralink_com_early(int silent)
/* reset */
r = sysctl_read(RA_SYSCTL_RST);
- r |= RST_UARTL;
+ r |= ra_uart2rst(RALINK_CONADDR);
sysctl_write(RA_SYSCTL_RST, r);
- r ^= RST_UARTL;
+ r ^= ra_uart2rst(RALINK_CONADDR);
sysctl_write(RA_SYSCTL_RST, r);
if (silent) {
@@ -317,12 +412,14 @@ ralink_com_early(int silent)
* effectively tri-stating the UARTL block
*/
r = sysctl_read(RA_SYSCTL_GPIOMODE);
- r |= GPIOMODE_UARTL;
+ r &= ra_uart2gpiomode(RALINK_CONADDR);
+ r |= __SHIFTIN(1, ra_uart2gpiomode(RALINK_CONADDR));
sysctl_write(RA_SYSCTL_GPIOMODE, r);
} else {
/* make sure we are in UART mode */
r = sysctl_read(RA_SYSCTL_GPIOMODE);
- r &= ~GPIOMODE_UARTL;
+ r &= ra_uart2gpiomode(RALINK_CONADDR);
+ r |= __SHIFTIN(0, ra_uart2gpiomode(RALINK_CONADDR));
sysctl_write(RA_SYSCTL_GPIOMODE, r);
}
@@ -331,16 +428,18 @@ ralink_com_early(int silent)
/* set baud rate */
uart_write(RA_UART_LCR,
- UART_LCR_WLS0 | UART_LCR_WLS1 | UART_LCR_DLAB);
+ UART_LCR_WLS0 | UART_LCR_WLS1 | UART_LCR_DLAB);
uart_write(RA_UART_DLL,
- (RA_UART_FREQ / RA_SERIAL_CLKDIV / RA_BAUDRATE)
- & 0xffff);
- uart_write(RA_UART_LCR,
- UART_LCR_WLS0 | UART_LCR_WLS1);
+ (RA_UART_FREQ / RA_SERIAL_CLKDIV / RA_BAUDRATE) & 0xffff);
+#if defined(MT7628)
+ uart_write(RA_UART_DLM,
+ ((RA_UART_FREQ / RA_SERIAL_CLKDIV / RA_BAUDRATE) & 0xffff) >> 8);
+#endif
+ uart_write(RA_UART_LCR, UART_LCR_WLS0 | UART_LCR_WLS1);
regs.cr_iot = &ra_bus_memt;
- regs.cr_iobase = RA_UART_LITE_BASE;
- regs.cr_nports = 0x1000;
+ regs.cr_iobase = RALINK_CONADDR;
+ regs.cr_nports = 32;
ralink_com_initmap(®s);
if ((error = bus_space_map(regs.cr_iot, regs.cr_iobase, regs.cr_nports,
@@ -348,7 +447,12 @@ ralink_com_early(int silent)
return;
}
+#if defined(MT7628)
+ comcnattach1(®s, RA_BAUDRATE, RA_UART_FREQ,
+ COM_TYPE_NORMAL, CONMODE);
+#else
/* Ralink UART has a 16-bit rate latch (like the AU1x00) */
comcnattach1(®s, RA_BAUDRATE, RA_UART_FREQ,
- COM_TYPE_AU1x00, CONMODE);
+ COM_TYPE_AU1x00, CONMODE);
+#endif
}
Index: src/sys/arch/mips/ralink/ralink_intr.c
diff -u src/sys/arch/mips/ralink/ralink_intr.c:1.4 src/sys/arch/mips/ralink/ralink_intr.c:1.5
--- src/sys/arch/mips/ralink/ralink_intr.c:1.4 Fri Aug 26 15:45:48 2016
+++ src/sys/arch/mips/ralink/ralink_intr.c Wed Oct 5 15:54:58 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: ralink_intr.c,v 1.4 2016/08/26 15:45:48 skrll Exp $ */
+/* $NetBSD: ralink_intr.c,v 1.5 2016/10/05 15:54:58 ryo Exp $ */
/*-
* Copyright (c) 2011 CradlePoint Technology, Inc.
* All rights reserved.
@@ -29,7 +29,7 @@
#define __INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ralink_intr.c,v 1.4 2016/08/26 15:45:48 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ralink_intr.c,v 1.5 2016/10/05 15:54:58 ryo Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -96,13 +96,6 @@ static const struct ipl_sr_map ralink_ip
* USB
*/
-
-/*
- * we use 5 MIPS cpu interrupts:
- * MIPS INT0 .. INT4
- */
-#define NCPUINTRS 5
-
struct ra_intr {
LIST_HEAD(, evbmips_intrhand) intr_list;
struct evcnt intr_evcnt;
@@ -115,26 +108,36 @@ struct ra_intr {
*/
static struct ra_intr ra_intrtab[RA_IRQ_MAX];
static const char * const ra_intr_names[RA_IRQ_MAX] = {
- "intr 0 (lowpri)",
- "intr 1 (highpri)",
- "intr 2 (pci)",
- "intr 3 (frame)",
- "intr 4 (wlan)",
- "intr 5 (timer)",
- "intr 0 (sysctl)",
- "intr 1 (timer0)",
- "intr 2 (watchdog)",
- "intr 3 (illacc)",
- "intr 4 (pcm)",
- "intr 5 (uartf)",
- "intr 6 (gpio)",
- "intr 7 (dma)",
- "intr 8 (nand)",
- "intr 9 (perf)",
- "intr 10 (i2s)",
- "intr 12 (uartl)",
- "intr 17 (ethsw)",
- "intr 18 (usb)"
+ /* CPU interrupts */
+ [RA_IRQ_LOW] = "intr 0 (lowpri)",
+ [RA_IRQ_HIGH] = "intr 1 (highpri)",
+ [RA_IRQ_PCI] = "intr 2 (pci)",
+ [RA_IRQ_FENGINE]= "intr 3 (frame)",
+ [RA_IRQ_WLAN] = "intr 4 (wlan)",
+ [RA_IRQ_TIMER] = "intr 5 (timer)",
+
+ /* Interrupt controller */
+ [RA_IRQ_SYSCTL] = "intc sysctl",
+ [RA_IRQ_TIMER0] = "intc timer0",
+ [RA_IRQ_WDOG] = "intc wdog",
+ [RA_IRQ_ILLACC] = "intc illacc",
+ [RA_IRQ_PCM] = "intc pcm",
+ [RA_IRQ_UARTF] = "intc uartf",
+ [RA_IRQ_PIO] = "intc gpio",
+ [RA_IRQ_DMA] = "intc dma",
+ [RA_IRQ_NAND] = "intc nand",
+ [RA_IRQ_PERF] = "intc pef",
+ [RA_IRQ_I2S] = "intc i2s",
+ [RA_IRQ_SPI] = "intc spi",
+ [RA_IRQ_UARTL] = "intc uartl",
+ [RA_IRQ_CRYPTO] = "intc crypto",
+ [RA_IRQ_SDHC] = "intc sdhc",
+ [RA_IRQ_R2P] = "intc r2p",
+ [RA_IRQ_ETHSW] = "intc ethsw",
+ [RA_IRQ_USB] = "intc usb",
+ [RA_IRQ_UDEV] = "intc udev",
+ [RA_IRQ_UART1] = "intc uart1",
+ [RA_IRQ_UART2] = "intc uart2",
};
/* determine if irq belongs to the PIC */
@@ -142,12 +145,69 @@ static const char * const ra_intr_names[
/* map the IRQ num to PIC reg bits */
static const uint8_t irq2bit[RA_IRQ_MAX] = {
- -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 17, 18
+ /* CPU interrupts */
+ [RA_IRQ_LOW] = -1,
+ [RA_IRQ_HIGH] = -1,
+ [RA_IRQ_PCI] = -1,
+ [RA_IRQ_FENGINE]= -1,
+ [RA_IRQ_WLAN] = -1,
+ [RA_IRQ_TIMER] = -1,
+
+ /* Interrupt controller */
+ [RA_IRQ_SYSCTL] = INT_SYSCTL,
+ [RA_IRQ_TIMER0] = INT_TIMER0,
+ [RA_IRQ_WDOG] = INT_WDOG,
+ [RA_IRQ_ILLACC] = INT_ILLACC,
+ [RA_IRQ_PCM] = INT_PCM,
+ [RA_IRQ_UARTF] = INT_UARTF,
+ [RA_IRQ_PIO] = INT_PIO,
+ [RA_IRQ_DMA] = INT_DMA,
+ [RA_IRQ_NAND] = INT_NAND,
+ [RA_IRQ_PERF] = INT_PERF,
+ [RA_IRQ_I2S] = INT_I2S,
+ [RA_IRQ_SPI] = INT_SPI,
+ [RA_IRQ_UARTL] = INT_UARTL,
+#ifdef INT_UART1
+ [RA_IRQ_UART1] = INT_UART1,
+#endif
+#ifdef INT_UART2
+ [RA_IRQ_UART2] = INT_UART2,
+#endif
+ [RA_IRQ_CRYPTO] = INT_CRYPTO,
+ [RA_IRQ_SDHC] = INT_SDHC,
+ [RA_IRQ_R2P] = INT_R2P,
+ [RA_IRQ_ETHSW] = INT_ETHSW,
+ [RA_IRQ_USB] = INT_USB,
+ [RA_IRQ_UDEV] = INT_UDEV
};
/* map the PIC reg bits to IRQ num */
-static const uint8_t bit2irq[19] = {
- 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 255, 17, 255, 255, 255, 255, 18, 19
+static const uint8_t bit2irq[32] = {
+ [INT_SYSCTL] = RA_IRQ_SYSCTL,
+ [INT_TIMER0] = RA_IRQ_TIMER0,
+ [INT_WDOG] = RA_IRQ_WDOG,
+ [INT_ILLACC] = RA_IRQ_ILLACC,
+ [INT_PCM] = RA_IRQ_PCM,
+ [INT_UARTF] = RA_IRQ_UARTF,
+ [INT_PIO] = RA_IRQ_PIO,
+ [INT_DMA] = RA_IRQ_DMA,
+ [INT_NAND] = RA_IRQ_NAND,
+ [INT_PERF] = RA_IRQ_PERF,
+ [INT_I2S] = RA_IRQ_I2S,
+ [INT_SPI] = RA_IRQ_SPI,
+ [INT_UARTL] = RA_IRQ_UARTL,
+#ifdef INT_UART1
+ [INT_UART1] = RA_IRQ_UART1,
+#endif
+#ifdef INT_UART2
+ [INT_UART2] = RA_IRQ_UART2,
+#endif
+ [INT_CRYPTO] = RA_IRQ_CRYPTO,
+ [INT_SDHC] = RA_IRQ_SDHC,
+ [INT_R2P] = RA_IRQ_R2P,
+ [INT_ETHSW] = RA_IRQ_ETHSW,
+ [INT_USB] = RA_IRQ_USB,
+ [INT_UDEV] = RA_IRQ_UDEV
};
@@ -174,12 +234,12 @@ evbmips_intr_init(void)
LIST_INIT(&ra_intrtab[irq].intr_list);
if (PIC_IRQ_P(irq)) {
evcnt_attach_dynamic(&ra_intrtab[irq].intr_evcnt,
- EVCNT_TYPE_INTR, NULL, "pic",
- ra_intr_names[irq]);
+ EVCNT_TYPE_INTR, NULL, "pic",
+ ra_intr_names[irq]);
} else {
evcnt_attach_dynamic(&ra_intrtab[irq].intr_evcnt,
- EVCNT_TYPE_INTR, NULL, "cpu0",
- ra_intr_names[irq]);
+ EVCNT_TYPE_INTR, NULL, "cpu0",
+ ra_intr_names[irq]);
}
}
@@ -188,9 +248,9 @@ evbmips_intr_init(void)
* but the block enabled
*/
intctl_write(RA_INTCTL_DISABLE, ~0);
- intctl_write(RA_INTCTL_ENABLE, INT_GLOBAL);
+ intctl_write(RA_INTCTL_ENABLE, INT_GLOBAL_EN);
- /*
+ /*
* establish the low/high priority cpu interrupts.
* note here we pass the value of the priority as the argument
* so it is passed to ra_pic_intr() correctly.
@@ -267,7 +327,7 @@ ra_pic_intr(void *arg)
{
const int priority = (intptr_t)arg;
const u_int off = (priority == 0) ?
- RA_INTCTL_IRQ0STAT : RA_INTCTL_IRQ1STAT;
+ RA_INTCTL_IRQ0STAT : RA_INTCTL_IRQ1STAT;
uint32_t pending = intctl_read(off);
while (pending != 0) {
Index: src/sys/arch/mips/ralink/ralink_mainbus.c
diff -u src/sys/arch/mips/ralink/ralink_mainbus.c:1.4 src/sys/arch/mips/ralink/ralink_mainbus.c:1.5
--- src/sys/arch/mips/ralink/ralink_mainbus.c:1.4 Wed Apr 30 00:52:49 2014
+++ src/sys/arch/mips/ralink/ralink_mainbus.c Wed Oct 5 15:54:58 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: ralink_mainbus.c,v 1.4 2014/04/30 00:52:49 matt Exp $ */
+/* $NetBSD: ralink_mainbus.c,v 1.5 2016/10/05 15:54:58 ryo Exp $ */
/*-
* Copyright (c) 2011 CradlePoint Technology, Inc.
* All rights reserved.
@@ -27,8 +27,9 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ralink_mainbus.c,v 1.4 2014/04/30 00:52:49 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ralink_mainbus.c,v 1.5 2016/10/05 15:54:58 ryo Exp $");
+#include "locators.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
@@ -124,6 +125,11 @@ mainbus_attach(device_t parent, device_t
static int
mainbus_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
{
+ struct mainbus_attach_args *ma;
+
+ ma = aux;
+ ma->ma_addr = cf->cf_loc[MAINBUSCF_ADDR];
+
if (config_match(parent, cf, aux) > 0)
config_attach(parent, cf, aux, mainbus_print);
else
@@ -134,9 +140,15 @@ mainbus_search(device_t parent, cfdata_t
int
mainbus_print(void *aux, const char *pnp)
{
+ struct mainbus_attach_args *ma;
+
if (pnp)
aprint_normal("%s unconfigured\n", pnp);
+ ma = aux;
+ if (ma->ma_addr != MAINBUSCF_ADDR_DEFAULT)
+ aprint_normal(" addr 0x%llx", ma->ma_addr);
+
return UNCONF;
}
@@ -168,8 +180,9 @@ mainbus_attach_critical(struct mainbus_s
cf = config_search_ia(mainbus_find, sc->sc_dev, "mainbus", &ma);
if (cf == NULL && critical_devs[i].required)
panic("%s: failed to find %s",
- __func__, critical_devs[i].name);
+ __func__, critical_devs[i].name);
+ ma.ma_addr = cf->cf_loc[MAINBUSCF_ADDR];
config_attach(sc->sc_dev, cf, &ma, mainbus_print);
}
}
Index: src/sys/arch/mips/ralink/ralink_eth.c
diff -u src/sys/arch/mips/ralink/ralink_eth.c:1.10 src/sys/arch/mips/ralink/ralink_eth.c:1.11
--- src/sys/arch/mips/ralink/ralink_eth.c:1.10 Wed Oct 5 15:39:31 2016
+++ src/sys/arch/mips/ralink/ralink_eth.c Wed Oct 5 15:54:58 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: ralink_eth.c,v 1.10 2016/10/05 15:39:31 ryo Exp $ */
+/* $NetBSD: ralink_eth.c,v 1.11 2016/10/05 15:54:58 ryo Exp $ */
/*-
* Copyright (c) 2011 CradlePoint Technology, Inc.
* All rights reserved.
@@ -29,7 +29,7 @@
/* ralink_eth.c -- Ralink Ethernet Driver */
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ralink_eth.c,v 1.10 2016/10/05 15:39:31 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ralink_eth.c,v 1.11 2016/10/05 15:54:58 ryo Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -95,7 +95,7 @@ struct ralink_rx_desc {
#define RXD_IP_VLD (1 << 31)
};
-/* PDMA RX Descriptor Format */
+/* PDMA TX Descriptor Format */
struct ralink_tx_desc {
uint32_t data_ptr0;
uint32_t txd_info1;
@@ -362,7 +362,12 @@ ralink_eth_attach(device_t parent, devic
* do some randomisation using the current uptime. It's not meant
* for anything but avoiding hard-coding an address.
*/
+#ifdef RALINK_ETH_MACADDR
+ uint8_t enaddr[ETHER_ADDR_LEN];
+ ether_aton_r(enaddr, sizeof(enaddr), ___STRING(RALINK_ETH_MACADDR));
+#else
uint8_t enaddr[ETHER_ADDR_LEN] = { 0x00, 0x30, 0x44, 0x00, 0x00, 0x00 };
+#endif
sc->sc_dev = self;
sc->sc_dmat = ma->ma_dmat;
@@ -480,7 +485,7 @@ ralink_eth_attach(device_t parent, devic
sc->sc_ethercom.ec_mii = &sc->sc_mii;
ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange,
ether_mediastatus);
- mii_attach(sc->sc_dev, &sc->sc_mii, ~0, i, MII_OFFSET_ANY,
+ mii_attach(sc->sc_dev, &sc->sc_mii, ~0, MII_PHY_ANY, MII_OFFSET_ANY,
MIIF_FORCEANEG|MIIF_DOPAUSE|MIIF_NOISOLATE);
if (LIST_EMPTY(&sc->sc_mii.mii_phys)) {
@@ -703,7 +708,7 @@ ralink_eth_reset(ralink_eth_softc_t *sc)
r ^= RST_FE;
sy_write(sc, RA_SYSCTL_RST, r);
- /* Wait until the PDMA is quiscent */
+ /* Wait until the PDMA is quiescent */
for (;;) {
r = fe_read(sc, RA_FE_PDMA_GLOBAL_CFG);
if (r & FE_PDMA_GLOBAL_CFG_RX_DMA_BUSY) {
@@ -732,7 +737,7 @@ ralink_eth_hw_init(ralink_eth_softc_t *s
/* reset to a known good state */
ralink_eth_reset(sc);
-#if defined(RT3050) || defined(RT3052)
+#if defined(RT3050) || defined(RT3052) || defined(MT7628)
/* Bring the switch to a sane default state (from linux driver) */
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_SGC2,
0x00000000);
@@ -746,6 +751,16 @@ ralink_eth_hw_init(ralink_eth_softc_t *s
0x00001001);
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PVIDC2,
0x00001001);
+#if defined(MT7628)
+ bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_VMSC0,
+ 0xffffffff);
+ bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_POC0,
+ 0x10007f7f);
+ bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_POC2,
+ 0x00007f7f);
+ bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_FTC2,
+ 0x0002500c);
+#else
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_VMSC0,
0xffff417e);
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_POC0,
@@ -754,6 +769,7 @@ ralink_eth_hw_init(ralink_eth_softc_t *s
0x00007f3f);
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_FTC2,
0x00d6500c);
+#endif
bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_SWGC,
0x0008a301); /* hashing algorithm=XOR48 */
/* aging interval=300sec */
@@ -870,6 +886,7 @@ ralink_eth_hw_init(ralink_eth_softc_t *s
fe_write(sc, RA_FE_PDMA_GLOBAL_CFG, r);
(void) fe_read(sc, RA_FE_PDMA_GLOBAL_CFG);
+#if !defined(MT7628)
/* Setup the PDMA VLAN ID's */
fe_write(sc, RA_FE_VLAN_ID_0001, 0x00010000);
fe_write(sc, RA_FE_VLAN_ID_0203, 0x00030002);
@@ -879,20 +896,25 @@ ralink_eth_hw_init(ralink_eth_softc_t *s
fe_write(sc, RA_FE_VLAN_ID_1011, 0x000b000a);
fe_write(sc, RA_FE_VLAN_ID_1213, 0x000d000c);
fe_write(sc, RA_FE_VLAN_ID_1415, 0x000f000e);
+#endif
/* Give the TX and TX rings to the chip. */
fe_write(sc, RA_FE_PDMA_TX0_PTR,
htole32(MIPS_KSEG0_TO_PHYS(&sc->sc_txdesc)));
fe_write(sc, RA_FE_PDMA_TX0_COUNT, htole32(RALINK_ETH_NUM_TX_DESC));
fe_write(sc, RA_FE_PDMA_TX0_CPU_IDX, 0);
+#if !defined(MT7628)
fe_write(sc, RA_FE_PDMA_RESET_IDX, PDMA_RST_TX0);
+#endif
fe_write(sc, RA_FE_PDMA_RX0_PTR,
htole32(MIPS_KSEG0_TO_PHYS(&sc->sc_rxdesc)));
fe_write(sc, RA_FE_PDMA_RX0_COUNT, htole32(RALINK_ETH_NUM_RX_DESC));
fe_write(sc, RA_FE_PDMA_RX0_CPU_IDX,
htole32(RALINK_ETH_NUM_RX_DESC - 1));
+#if !defined(MT7628)
fe_write(sc, RA_FE_PDMA_RESET_IDX, PDMA_RST_RX0);
+#endif
fe_write(sc, RA_FE_PDMA_RX0_CPU_IDX,
htole32(RALINK_ETH_NUM_RX_DESC - 1));
@@ -904,14 +926,28 @@ ralink_eth_hw_init(ralink_eth_softc_t *s
FE_PDMA_GLOBAL_CFG_BURST_SZ_4);
/* Setup the clock for the Frame Engine */
+#if defined(MT7628)
+ fe_write(sc, RA_FE_SDM_CON, 0x8100);
+#else
fe_write(sc, RA_FE_GLOBAL_CFG,
FE_GLOBAL_CFG_EXT_VLAN(0x8100) |
FE_GLOBAL_CFG_US_CLK(RA_BUS_FREQ / 1000000) |
FE_GLOBAL_CFG_L2_SPACE(0x8));
+#endif
/* Turn on all interrupts */
+#if defined(MT7628)
+ fe_write(sc, RA_FE_INT_MASK,
+ RA_FE_INT_RX_DONE_INT1 |
+ RA_FE_INT_RX_DONE_INT0 |
+ RA_FE_INT_TX_DONE_INT3 |
+ RA_FE_INT_TX_DONE_INT2 |
+ RA_FE_INT_TX_DONE_INT1 |
+ RA_FE_INT_TX_DONE_INT0);
+#else
fe_write(sc, RA_FE_INT_ENABLE,
FE_INT_RX | FE_INT_TX3 | FE_INT_TX2 | FE_INT_TX1 | FE_INT_TX0);
+#endif
/*
* Configure GDMA forwarding
@@ -922,21 +958,34 @@ ralink_eth_hw_init(ralink_eth_softc_t *s
fe_write(sc, RA_FE_GDMA1_FWD_CFG,
(FE_GDMA_FWD_CFG_DIS_TX_CRC | FE_GDMA_FWD_CFG_DIS_TX_PAD));
#endif
+
+#if !defined(MT7628)
fe_write(sc, RA_FE_GDMA1_FWD_CFG,
FE_GDMA_FWD_CFG_JUMBO_LEN(MCLBYTES/1024) |
FE_GDMA_FWD_CFG_STRIP_RX_CRC |
FE_GDMA_FWD_CFG_IP4_CRC_EN |
FE_GDMA_FWD_CFG_TCP_CRC_EN |
FE_GDMA_FWD_CFG_UDP_CRC_EN);
+#endif
/* CDMA also needs CRCs turned on */
+#if !defined(MT7628)
r = fe_read(sc, RA_FE_CDMA_CSG_CFG);
r |= (FE_CDMA_CSG_CFG_IP4_CRC_EN | FE_CDMA_CSG_CFG_UDP_CRC_EN |
FE_CDMA_CSG_CFG_TCP_CRC_EN);
fe_write(sc, RA_FE_CDMA_CSG_CFG, r);
+#endif
/* Configure Flow Control Thresholds */
-#ifdef RT3883
+#if defined(MT7628)
+ sw_write(sc, RA_ETH_SW_FCT0,
+ RA_ETH_SW_FCT0_FC_RLS_TH(0xc8) |
+ RA_ETH_SW_FCT0_FC_SET_TH(0xa0) |
+ RA_ETH_SW_FCT0_DROP_RLS_TH(0x78) |
+ RA_ETH_SW_FCT0_DROP_SET_TH(0x50));
+ sw_write(sc, RA_ETH_SW_FCT1,
+ RA_ETH_SW_FCT1_PORT_TH(0x14));
+#elif defined(RT3883)
fe_write(sc, RA_FE_PSE_FQ_CFG,
FE_PSE_FQ_MAX_COUNT(0xff) |
FE_PSE_FQ_FC_RELEASE(0x90) |
@@ -949,8 +998,12 @@ ralink_eth_hw_init(ralink_eth_softc_t *s
#endif
#ifdef RALINK_ETH_DEBUG
+#ifdef RA_FE_MDIO_CFG1
printf("FE_MDIO_CFG1: 0x%08x\n", fe_read(sc, RA_FE_MDIO_CFG1));
+#endif
+#ifdef RA_FE_MDIO_CFG2
printf("FE_MDIO_CFG2: 0x%08x\n", fe_read(sc, RA_FE_MDIO_CFG2));
+#endif
printf("FE_PDMA_TX0_PTR: %08x\n", fe_read(sc, RA_FE_PDMA_TX0_PTR));
printf("FE_PDMA_TX0_COUNT: %08x\n",
fe_read(sc, RA_FE_PDMA_TX0_COUNT));
@@ -967,16 +1020,27 @@ ralink_eth_hw_init(ralink_eth_softc_t *s
fe_read(sc, RA_FE_PDMA_RX0_DMA_IDX));
printf("FE_PDMA_GLOBAL_CFG: %08x\n",
fe_read(sc, RA_FE_PDMA_GLOBAL_CFG));
+#ifdef RA_FE_GLOBAL_CFG
printf("FE_GLOBAL_CFG: %08x\n", fe_read(sc, RA_FE_GLOBAL_CFG));
+#endif
+#ifdef RA_FE_GDMA1_FWD_CFG
printf("FE_GDMA1_FWD_CFG: %08x\n",
fe_read(sc, RA_FE_GDMA1_FWD_CFG));
+#endif
+#ifdef RA_FE_CDMA_CSG_CFG
printf("FE_CDMA_CSG_CFG: %08x\n", fe_read(sc, RA_FE_CDMA_CSG_CFG));
+#endif
+#ifdef RA_FE_PSE_FQ_CFG
printf("FE_PSE_FQ_CFG: %08x\n", fe_read(sc, RA_FE_PSE_FQ_CFG));
#endif
+#endif
/* Force PSE Reset to get everything finalized */
+#if defined(MT7628)
+#else
fe_write(sc, RA_FE_GLOBAL_RESET, FE_GLOBAL_RESET_PSE);
fe_write(sc, RA_FE_GLOBAL_RESET, 0);
+#endif
}
/*
@@ -1351,7 +1415,22 @@ ralink_eth_intr(void *arg)
fe_write(sc, RA_FE_INT_STATUS, ~0);
RALINK_DEBUG(RALINK_DEBUG_REG,"%s() status: 0x%08x\n",
__func__, status);
+#if defined(MT7628)
+ if ((status & (RA_FE_INT_RX_DONE_INT1 | RA_FE_INT_RX_DONE_INT0 |
+ RA_FE_INT_TX_DONE_INT3 | RA_FE_INT_TX_DONE_INT2 |
+ RA_FE_INT_TX_DONE_INT1 | RA_FE_INT_TX_DONE_INT0)) == 0) {
+ if (n == 0)
+ sc->sc_evcnt_spurious_intr.ev_count++;
+ return (n != 0);
+ }
+
+ if (status & (RA_FE_INT_RX_DONE_INT1|RA_FE_INT_RX_DONE_INT0))
+ ralink_eth_rxintr(sc);
+ if (status & (RA_FE_INT_TX_DONE_INT3 | RA_FE_INT_TX_DONE_INT2 |
+ RA_FE_INT_TX_DONE_INT1 | RA_FE_INT_TX_DONE_INT0))
+ ralink_eth_txintr(sc);
+#else
if ((status & (FE_INT_RX | FE_INT_TX0)) == 0) {
if (n == 0)
sc->sc_evcnt_spurious_intr.ev_count++;
@@ -1363,6 +1442,7 @@ ralink_eth_intr(void *arg)
if (status & FE_INT_TX0)
ralink_eth_txintr(sc);
+#endif
}
/* Try to get more packets going. */
@@ -1539,7 +1619,7 @@ ralink_eth_txintr(ralink_eth_softc_t *sc
break;
RALINK_DEBUG(RALINK_DEBUG_REG,"-tx(%d) transmitted\n",
- txs->txs_idx);
+ txs->txs_idx);
SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
@@ -1564,7 +1644,7 @@ ralink_eth_txintr(ralink_eth_softc_t *sc
/*
* ralink_eth_mdio_enable
*/
-#if defined (RT3050) || defined(RT3052)
+#if defined(RT3050) || defined(RT3052)
static void
ralink_eth_mdio_enable(ralink_eth_softc_t *sc, bool enable)
{
@@ -1621,7 +1701,7 @@ ralink_eth_mii_read(device_t self, int p
#if 0
printf("%s() phy_addr: %d phy_reg: %d\n", __func__, phy_addr, phy_reg);
#endif
-#if defined(RT3050) || defined(RT3052)
+#if defined(RT3050) || defined(RT3052) || defined(MT7628)
if (phy_addr > 5)
return 0;
#endif
@@ -1635,7 +1715,7 @@ ralink_eth_mii_read(device_t self, int p
*/
for (;;) {
/* rd_rdy: read operation is complete */
-#if defined(RT3050) || defined(RT3052)
+#if defined(RT3050) || defined(RT3052) || defined(MT7628)
if ((sw_read(sc, RA_ETH_SW_PCTL1) & PCTL1_RD_DONE) == 0)
break;
#else
@@ -1644,7 +1724,7 @@ ralink_eth_mii_read(device_t self, int p
#endif
}
-#if defined(RT3050) || defined(RT3052)
+#if defined(RT3050) || defined(RT3052) || defined(MT7628)
sw_write(sc, RA_ETH_SW_PCTL0,
PCTL0_RD_CMD | PCTL0_REG(phy_reg) | PCTL0_ADDR(phy_addr));
#else
@@ -1660,7 +1740,7 @@ ralink_eth_mii_read(device_t self, int p
* TODO: timeout (linux uses jiffies to measure 5 seconds)
*/
for (;;) {
-#if defined(RT3050) || defined(RT3052)
+#if defined(RT3050) || defined(RT3052) || defined(MT7628)
if ((sw_read(sc, RA_ETH_SW_PCTL1) & PCTL1_RD_DONE) != 0) {
int data = PCTL1_RD_VAL(
sw_read(sc, RA_ETH_SW_PCTL1));
@@ -1697,7 +1777,7 @@ ralink_eth_mii_write(device_t self, int
* TODO: timeout (linux uses jiffies to measure 5 seconds)
*/
for (;;) {
-#if defined(RT3050) || defined(RT3052)
+#if defined(RT3050) || defined(RT3052) || defined(MT7628)
if ((sw_read(sc, RA_ETH_SW_PCTL1) & PCTL1_RD_DONE) == 0)
break;
#else
@@ -1706,7 +1786,7 @@ ralink_eth_mii_write(device_t self, int
#endif
}
-#if defined(RT3050) || defined(RT3052)
+#if defined(RT3050) || defined(RT3052) || defined(MT7628)
sw_write(sc, RA_ETH_SW_PCTL0,
PCTL0_WR_CMD | PCTL0_WR_VAL(val) | PCTL0_REG(phy_reg) |
PCTL0_ADDR(phy_addr));
@@ -1723,7 +1803,7 @@ ralink_eth_mii_write(device_t self, int
/* make sure write operation is complete */
for (;;) {
-#if defined(RT3050) || defined(RT3052)
+#if defined(RT3050) || defined(RT3052) || defined(MT7628)
if ((sw_read(sc, RA_ETH_SW_PCTL1) & PCTL1_WR_DONE) != 0) {
ralink_eth_mdio_enable(sc, false);
return;
Index: src/sys/arch/mips/ralink/ralink_gpio.c
diff -u src/sys/arch/mips/ralink/ralink_gpio.c:1.5 src/sys/arch/mips/ralink/ralink_gpio.c:1.6
--- src/sys/arch/mips/ralink/ralink_gpio.c:1.5 Wed Mar 12 22:21:07 2014
+++ src/sys/arch/mips/ralink/ralink_gpio.c Wed Oct 5 15:54:58 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: ralink_gpio.c,v 1.5 2014/03/12 22:21:07 mrg Exp $ */
+/* $NetBSD: ralink_gpio.c,v 1.6 2016/10/05 15:54:58 ryo Exp $ */
/*-
* Copyright (c) 2011 CradlePoint Technology, Inc.
* All rights reserved.
@@ -29,7 +29,7 @@
/* ra_gpio.c -- Ralink 3052 gpio driver */
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ralink_gpio.c,v 1.5 2014/03/12 22:21:07 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ralink_gpio.c,v 1.6 2016/10/05 15:54:58 ryo Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -46,10 +46,12 @@ __KERNEL_RCSID(0, "$NetBSD: ralink_gpio.
#include <sys/gpio.h>
#include <dev/gpio/gpiovar.h>
-#define SLICKROCK
-
#include <mips/ralink/ralink_reg.h>
#include <mips/ralink/ralink_var.h>
+
+#if !defined(MT7628)
+#define SLICKROCK
+#endif
#include <mips/ralink/ralink_gpio.h>
#if 0
@@ -88,6 +90,10 @@ __KERNEL_RCSID(0, "$NetBSD: ralink_gpio.
* 1 - 2 I2C (I2C_SCLK/I2C_SD pins)
*/
+#ifdef MT7628
+#define GPIO_PINS 96
+#define SPECIAL_COMMANDS 0
+#else
#if defined(SLICKROCK)
#define GPIO_PINS 96
#else
@@ -100,19 +106,59 @@ __KERNEL_RCSID(0, "$NetBSD: ralink_gpio.
#define BOOT_COUNT GPIO_PINS
#define UPGRADE (BOOT_COUNT + 1)
#define SPECIAL_COMMANDS (UPGRADE + 1 - GPIO_PINS)
+#endif
+
/*
* The pin_share array maps to the highest pin used for each of the 10
* GPIO mode bit settings.
*/
+#if defined(MT7628)
+const static struct {
+ int pin_start;
+ int pin_end;
+ uint32_t sysreg;
+ uint32_t regmask;
+ uint32_t mode;
+} gpio_mux_map[] = {
+ { 0, 3, RA_SYSCTL_GPIO1MODE, GPIO1MODE_I2S, 1 },
+ { 4, 5, RA_SYSCTL_GPIO1MODE, GPIO1MODE_I2C, 1 },
+ { 6, 6, RA_SYSCTL_GPIO1MODE, GPIO1MODE_SPI_CS1, 1 },
+ { 7, 10, RA_SYSCTL_GPIO1MODE, GPIO1MODE_SPI, 1 },
+ { 11, 11, RA_SYSCTL_GPIO1MODE, GPIO1MODE_GPIO, 1 },
+ { 12, 13, RA_SYSCTL_GPIO1MODE, GPIO1MODE_UART0, 1 },
+ { 14, 17, RA_SYSCTL_GPIO1MODE, GPIO1MODE_SPIS, 1 },
+ { 18, 18, RA_SYSCTL_GPIO1MODE, GPIO1MODE_PWM0, 1 },
+ { 19, 19, RA_SYSCTL_GPIO1MODE, GPIO1MODE_PWM1, 1 },
+ { 20, 21, RA_SYSCTL_GPIO1MODE, GPIO1MODE_UART2, 1 },
+ { 22, 29, RA_SYSCTL_GPIO1MODE, GPIO1MODE_SD, 1 },
+ { 30, 30, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P4_LED_KN, 1 },
+ { 31, 31, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P3_LED_KN, 1 },
+ { 32, 32, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P2_LED_KN, 1 },
+ { 33, 33, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P1_LED_KN, 1 },
+ { 34, 34, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P0_LED_KN, 1 },
+ { 35, 35, RA_SYSCTL_GPIO2MODE, GPIO2MODE_WLED_KN, 1 },
+ { 36, 36, RA_SYSCTL_GPIO1MODE, GPIO1MODE_PERST, 1 },
+ { 37, 37, RA_SYSCTL_GPIO1MODE, GPIO1MODE_REFCLK, 1 },
+ { 38, 38, RA_SYSCTL_GPIO1MODE, GPIO1MODE_WDT, 1 },
+ { 39, 39, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P4_LED_AN, 1 },
+ { 40, 40, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P3_LED_AN, 1 },
+ { 41, 41, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P2_LED_AN, 1 },
+ { 42, 42, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P1_LED_AN, 1 },
+ { 43, 43, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P0_LED_AN, 1 },
+ { 44, 44, RA_SYSCTL_GPIO2MODE, GPIO2MODE_WLED_AN, 1 },
+ { 45, 45, RA_SYSCTL_GPIO1MODE, GPIO1MODE_UART1, 1 },
+ { 46, 46, RA_SYSCTL_GPIO1MODE, GPIO1MODE_UART1, 1 },
+};
+#else
#if defined(SLICKROCK)
#define SR_GPIO_MODE 0xc1c1f
#else
-#define GPIO_MODE_SETTINGS 10
-const static u_int8_t pin_share[GPIO_MODE_SETTINGS] = {
+const static u_int8_t pin_share[] = {
2, 6, 9, 14, 14, 16, 21, 23, 39, 51
};
#endif
+#endif /* MT7628 */
#define DEBOUNCE_TIME 150 /* Milliseconds */
@@ -264,13 +310,19 @@ typedef struct ra_gpio_softc {
struct callout sc_tick_callout; /* For debouncing inputs */
- /*
+ /*
* These track gpio pins that have interrupted
*/
+#if defined(MT7628)
+ uint32_t sc_intr_status00_31;
+ uint32_t sc_intr_status32_63;
+ uint32_t sc_intr_status64_95;
+#else
uint32_t sc_intr_status00_23;
uint32_t sc_intr_status24_39;
uint32_t sc_intr_status40_51;
uint32_t sc_intr_status72_95;
+#endif
} ra_gpio_softc_t;
@@ -321,6 +373,38 @@ typedef struct pin_tab {
* instead of lots of if/then/else test & branching
*/
static const pin_tab_t pin_tab[] = {
+#if defined(MT7628)
+ {
+ 0, 31, 0, 0xffffffff,
+ RA_PIO_00_31_DATA,
+ RA_PIO_00_31_CLR_BIT,
+ RA_PIO_00_31_SET_BIT,
+ { 0xffffffff, RA_PIO_00_31_DIR },
+ { 0xffffffff, RA_PIO_00_31_INT_RISE_EN },
+ { 0xffffffff, RA_PIO_00_31_INT_FALL_EN },
+ { 0xffffffff, RA_PIO_00_31_POLARITY }
+ },
+ {
+ 32, 63, 32, 0xffffffff,
+ RA_PIO_32_63_DATA,
+ RA_PIO_32_63_CLR_BIT,
+ RA_PIO_32_63_SET_BIT,
+ { 0xffffffff, RA_PIO_32_63_DIR },
+ { 0xffffffff, RA_PIO_32_63_INT_RISE_EN },
+ { 0xffffffff, RA_PIO_32_63_INT_FALL_EN },
+ { 0xffffffff, RA_PIO_32_63_POLARITY }
+ },
+ {
+ 64, 95, 64, 0xffffffff,
+ RA_PIO_64_95_DATA,
+ RA_PIO_64_95_CLR_BIT,
+ RA_PIO_64_95_SET_BIT,
+ { 0xffffffff, RA_PIO_64_95_DIR },
+ { 0xffffffff, RA_PIO_64_95_INT_RISE_EN },
+ { 0xffffffff, RA_PIO_64_95_INT_FALL_EN },
+ { 0xffffffff, RA_PIO_64_95_POLARITY }
+ }
+#else
{
0, 24, 0, GPIO_PIN_MASK,
RA_PIO_00_23_DATA,
@@ -363,6 +447,7 @@ static const pin_tab_t pin_tab[] = {
{ GPIO_POL_MASK_72_95, RA_PIO_72_95_POLARITY, },
},
#endif
+#endif
};
/*
@@ -370,6 +455,15 @@ static const pin_tab_t pin_tab[] = {
* for a given pin. -1 means there is no pin there.
*/
static const int pin_tab_index[GPIO_PINS] = {
+#if defined(MT7628)
+/* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 */
+/* 0 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+/* 16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+/* 32 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+/* 48 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+/* 64 */ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+/* 80 */ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2
+#else /* !MT7628 */
/* 0 1 2 3 4 5 6 7 8 9 */
/* 0 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* 10 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -385,6 +479,7 @@ static const int pin_tab_index[GPIO_PINS
/* 80 */ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
/* 90 */ 3, 3, 3, 3, 3, 3
#endif
+#endif /* !MT7628 */
};
CFATTACH_DECL_NEW(rgpio, sizeof(struct ra_gpio_softc), ra_gpio_match,
@@ -412,7 +507,7 @@ static inline uint32_t
sy_read(ra_gpio_softc_t *sc, bus_size_t off)
{
KASSERTMSG((off & 3) == 0, "%s: unaligned off=%#" PRIxBUSSIZE "\n",
- __func__, off);
+ __func__, off);
return bus_space_read_4(sc->sc_memt, sc->sc_sy_memh, off);
}
@@ -420,7 +515,7 @@ static inline void
sy_write(ra_gpio_softc_t *sc, bus_size_t off, uint32_t val)
{
KASSERTMSG((off & 3) == 0, "%s: unaligned off=%#" PRIxBUSSIZE "\n",
- __func__, off);
+ __func__, off);
bus_space_write_4(sc->sc_memt, sc->sc_sy_memh, off, val);
}
@@ -428,7 +523,7 @@ static inline uint32_t
gp_read(ra_gpio_softc_t *sc, bus_size_t off)
{
KASSERTMSG((off & 3) == 0, "%s: unaligned off=%#" PRIxBUSSIZE "\n",
- __func__, off);
+ __func__, off);
return bus_space_read_4(sc->sc_memt, sc->sc_gp_memh, off);
}
@@ -436,7 +531,7 @@ static inline void
gp_write(ra_gpio_softc_t *sc, bus_size_t off, uint32_t val)
{
KASSERTMSG((off & 3) == 0, "%s: unaligned off=%#" PRIxBUSSIZE "\n",
- __func__, off);
+ __func__, off);
bus_space_write_4(sc->sc_memt, sc->sc_gp_memh, off, val);
}
@@ -511,6 +606,27 @@ ra_gpio_attach(device_t parent, device_t
}
/* Reset some registers */
+#if defined(MT7628)
+ gp_write(sc, RA_PIO_00_31_INT_RISE_EN, 0xffffffff);
+ gp_write(sc, RA_PIO_00_31_INT_FALL_EN, 0xffffffff);
+ gp_write(sc, RA_PIO_00_31_INT_HIGH_EN, 0);
+ gp_write(sc, RA_PIO_00_31_INT_LOW_EN, 0);
+
+ gp_write(sc, RA_PIO_32_63_INT_RISE_EN, 0xffffffff);
+ gp_write(sc, RA_PIO_32_63_INT_FALL_EN, 0xffffffff);
+ gp_write(sc, RA_PIO_32_63_INT_HIGH_EN, 0);
+ gp_write(sc, RA_PIO_32_63_INT_LOW_EN, 0);
+
+ gp_write(sc, RA_PIO_64_95_INT_RISE_EN, 0xffffffff);
+ gp_write(sc, RA_PIO_64_95_INT_FALL_EN, 0xffffffff);
+ gp_write(sc, RA_PIO_64_95_INT_HIGH_EN, 0);
+ gp_write(sc, RA_PIO_64_95_INT_LOW_EN, 0);
+
+ gp_write(sc, RA_PIO_00_31_POLARITY, 0);
+ gp_write(sc, RA_PIO_32_63_POLARITY, 0);
+ gp_write(sc, RA_PIO_64_95_POLARITY, 0);
+
+#else
gp_write(sc, RA_PIO_00_23_INT, 0xffffff);
gp_write(sc, RA_PIO_00_23_EDGE_INT, 0xffffff);
gp_write(sc, RA_PIO_24_39_INT, 0xffff);
@@ -522,6 +638,7 @@ ra_gpio_attach(device_t parent, device_t
gp_write(sc, RA_PIO_72_95_INT, 0xffffff);
gp_write(sc, RA_PIO_72_95_EDGE_INT, 0xffffff);
#endif
+#endif
/* Set up for interrupt handling, low priority interrupt queue */
sc->sc_ih = ra_intr_establish(RA_IRQ_PIO,
@@ -562,7 +679,7 @@ ra_gpio_attach(device_t parent, device_t
gpio_reset_registers(sc);
/* Initialize the GPIO pins */
- for (int pin=0; pin < GPIO_PINS; pin++)
+ for (int pin = 0; pin < GPIO_PINS; pin++)
ra_gpio_pin_init(sc, pin);
#if 0
@@ -621,10 +738,14 @@ ra_gpio_attach(device_t parent, device_t
gp_write(sc, RA_PIO_72_95_EDGE_INT, 0xffffff);
#endif
+#ifdef BOOT_COUNT
sc->sc_pins[BOOT_COUNT].pin_flags = GPIO_PIN_OUTPUT;
sc->sc_pins[BOOT_COUNT].pin_mapped = 0;
+#endif
+#ifdef UPGRADE
sc->sc_pins[UPGRADE].pin_flags = GPIO_PIN_OUTPUT;
sc->sc_pins[UPGRADE].pin_mapped = 0;
+#endif
gba.gba_gc = &sc->sc_gc;
gba.gba_pins = sc->sc_pins;
@@ -692,6 +813,23 @@ ra_gpio_pin_init(ra_gpio_softc_t *sc, in
GPIO_PIN_INVIN | GPIO_PIN_INVOUT;
sc->sc_pins[pin].pin_state = GPIO_PIN_INPUT;
+#if defined(MT7628)
+ /*
+ * Set the SYSCTL_GPIO{1,2}MODE register
+ * for the PIO block of any mapped GPIO
+ */
+ for (int i = 0; i < __arraycount(gpio_mux_map); i++) {
+ if ((pin >= gpio_mux_map[i].pin_start) &&
+ (pin >= gpio_mux_map[i].pin_end)) {
+ r = sy_read(sc, gpio_mux_map[i].sysreg);
+ r &= ~gpio_mux_map[i].regmask;
+ r |= __SHIFTIN(gpio_mux_map[i].mode,
+ gpio_mux_map[i].regmask);
+ sy_write(sc, gpio_mux_map[i].sysreg, r);
+ break;
+ }
+ }
+#else
#if defined(SLICKROCK)
r = sy_read(sc, RA_SYSCTL_GPIOMODE);
r |= SR_GPIO_MODE;
@@ -704,9 +842,10 @@ ra_gpio_pin_init(ra_gpio_softc_t *sc, in
* GPIO0 doesn't have an associated MODE register.
*/
if (pin != 0) {
- u_int gpio_mode = 0;
+ u_int gpio_mode;
- for (gpio_mode; gpio_mode < GPIO_MODE_SETTINGS; gpio_mode++) {
+ for (gpio_mode = 0; gpio_mode < __arraycount(pin_share);
+ gpio_mode++) {
if (pin <= pin_share[gpio_mode]) {
r = sy_read(sc, RA_SYSCTL_GPIOMODE);
if (10 == pin) {
@@ -724,7 +863,8 @@ ra_gpio_pin_init(ra_gpio_softc_t *sc, in
}
}
}
-#endif
+#endif /* SLICKROCK */
+#endif /* !MT7628 */
/* set direction */
RA_GPIO_PIN_INIT_DIR(sc, r, pin, ptp);
@@ -778,11 +918,13 @@ ra_gpio_pin_read(void *arg, int pin)
* Special hack: a pseudo-pin used for signaling
*/
rv = 0;
- switch(pin) {
+ switch (pin) {
+#ifdef BOOT_COUNT
case BOOT_COUNT:
if (1 == ra_check_memo_reg(NO_SECURITY))
rv = 1;
break;
+#endif
default:
#ifdef DIAGNOSTIC
aprint_normal_dev(sc->sc_dev, "%s: bad pin=%d\n",
@@ -817,7 +959,9 @@ ra_gpio_pin_write(void *arg, int pin, in
{
RALINK_DEBUG_FUNC_ENTRY();
ra_gpio_softc_t * const sc = arg;
+#if defined(BOOT_COUNT) || defined(UPGRADE)
uint32_t r;
+#endif
KASSERT(sc != NULL);
RALINK_DEBUG(RALINK_DEBUG_INFO, "pin %d, val %d\n", pin, value);
@@ -827,17 +971,21 @@ ra_gpio_pin_write(void *arg, int pin, in
* Special hack: a pseudo-pin used for signaling
*/
switch(pin) {
+#ifdef BOOT_COUNT
case BOOT_COUNT:
/* Reset boot count */
r = sy_read(sc, RA_SYSCTL_MEMO0);
if (r == MAGIC)
sy_write(sc, RA_SYSCTL_MEMO1, 0);
break;
+#endif
+#ifdef UPGRADE
case UPGRADE:
/* Set upgrade flag */
sy_write(sc, RA_SYSCTL_MEMO0, UPGRADE_MAGIC);
sy_write(sc, RA_SYSCTL_MEMO1, UPGRADE_MAGIC);
break;
+#endif
default:
#ifdef DIAGNOSTIC
aprint_normal_dev(sc->sc_dev, "%s: bad pin=%d\n",
@@ -846,7 +994,7 @@ ra_gpio_pin_write(void *arg, int pin, in
}
return;
}
-
+
/*
* normal case: a regular GPIO pin
* if pin number is in a gap in the range,
@@ -901,26 +1049,47 @@ ra_gpio_intr(void *arg)
#if 0
/* Read the 3 interrupt registers */
+#if defined(MT7628)
+ if (sc->sc_intr_status00_31 || sc->sc_intr_status32_63 ||
+ sc->sc_intr_status64_95) {
+ printf("\n0-31 %x, 32-63 %x, 64_95 %x\n",
+ sc->sc_intr_status00_31,
+ sc->sc_intr_status32_63,
+ sc->sc_intr_status64_95);
+ }
+#else
if (sc->sc_intr_status00_23 || sc->sc_intr_status24_39 ||
sc->sc_intr_status40_51) {
printf("\n0-23 %x, 24-39 %x, 40_51 %x\n",
- sc->sc_intr_status00_23,
- sc->sc_ntr_status24_39,
- sc->sc_ntr_status40_51);
+ sc->sc_intr_status00_23,
+ sc->sc_intr_status24_39,
+ sc->sc_intr_status40_51);
}
#endif
+#endif
+#if defined(MT7628)
+ sc->sc_intr_status00_31 |= gp_read(sc, RA_PIO_00_31_INT_STAT);
+ sc->sc_intr_status32_63 |= gp_read(sc, RA_PIO_32_63_INT_STAT);
+ sc->sc_intr_status64_95 |= gp_read(sc, RA_PIO_64_95_INT_STAT);
+#else
sc->sc_intr_status00_23 |= gp_read(sc, RA_PIO_00_23_INT);
sc->sc_intr_status24_39 |= gp_read(sc, RA_PIO_24_39_INT);
sc->sc_intr_status40_51 |= gp_read(sc, RA_PIO_40_51_INT);
#if defined(SLICKROCK)
sc->sc_intr_status72_95 |= gp_read(sc, RA_PIO_72_95_INT);
#endif
+#endif
#if 0
/* Trivial error checking, some interrupt had to have fired */
+#if defined(MT7628)
+ KASSERT((sc->sc_intr_status00_31 | sc->sc_intr_status32_64 |
+ sc->sc_intr_status64_95) != 0);
+#else
KASSERT((sc->sc_intr_status00_23 | sc->sc_intr_status24_39 |
- sc->sc_intr_status40_51) != 0);
+ sc->sc_intr_status40_51) != 0);
+#endif
#endif
/* Debounce interrupt */
@@ -933,6 +1102,19 @@ ra_gpio_intr(void *arg)
* I don't know if resetting the EDGE register is
* necessary, but the Ralink Linux driver does it.
*/
+#if defined(MT7628)
+ gp_write(sc, RA_PIO_00_31_INT_STAT, sc->sc_intr_status00_31);
+ gp_write(sc, RA_PIO_00_31_INT_STAT_EDGE, sc->sc_intr_status00_31);
+ gp_write(sc, RA_PIO_32_63_INT_STAT, sc->sc_intr_status32_63);
+ gp_write(sc, RA_PIO_32_63_INT_STAT_EDGE, sc->sc_intr_status32_63);
+ gp_write(sc, RA_PIO_64_95_INT_STAT, sc->sc_intr_status64_95);
+ gp_write(sc, RA_PIO_64_95_INT_STAT_EDGE, sc->sc_intr_status64_95);
+
+ /* Reset until next time */
+ sc->sc_intr_status00_31 = 0;
+ sc->sc_intr_status32_63 = 0;
+ sc->sc_intr_status64_95 = 0;
+#else
gp_write(sc, RA_PIO_00_23_INT, sc->sc_intr_status00_23);
gp_write(sc, RA_PIO_00_23_EDGE_INT, sc->sc_intr_status00_23);
gp_write(sc, RA_PIO_24_39_INT, sc->sc_intr_status24_39);
@@ -949,6 +1131,7 @@ ra_gpio_intr(void *arg)
sc->sc_intr_status24_39 = 0;
sc->sc_intr_status40_51 = 0;
sc->sc_intr_status72_95 = 0;
+#endif /* MT7628 */
return 1;
}
@@ -980,19 +1163,19 @@ ra_gpio_debounce_pin(ra_gpio_softc_t *sc
case SOFT_RST_IN_BUTTON:
KNOTE(&knotes, RESET_BUTTON_EVT);
break;
-
+
case SS_BUTTON:
KNOTE(&knotes, SS_BUTTON_EVT);
break;
-
+
case WPS_BUTTON:
KNOTE(&knotes, WPS_BUTTON_EVT);
break;
-
+
case WIFI_ENABLE:
KNOTE(&knotes, WIFI_ENABLE_EVT);
break;
-
+
/*
* These events are in case of overcurrent
* on USB/ExpressCard devices.
@@ -1047,7 +1230,7 @@ ra_gpio_debounce_pin(ra_gpio_softc_t *sc
default:
printf("\nUnknown debounce pin %d received.\n",
- debounce_pin[pin]);
+ debounce_pin[pin]);
}
#endif/* SLICKROCK */
#if defined(PEBBLES500) || defined(PEBBLES35)
@@ -1055,15 +1238,15 @@ ra_gpio_debounce_pin(ra_gpio_softc_t *sc
case SOFT_RST_IN_BUTTON:
KNOTE(&knotes, RESET_BUTTON_EVT);
break;
-
+
case WPS_BUTTON:
KNOTE(&knotes, WPS_BUTTON_EVT);
break;
-
+
case EXCARD_ATTACH:
KNOTE(&knotes, EXCARD_ATTACH_EVT);
break;
-
+
/*
* These events are in case of overcurrent
* on USB/ExpressCard devices.
@@ -1085,7 +1268,7 @@ ra_gpio_debounce_pin(ra_gpio_softc_t *sc
case CURRENT_LIMIT_FLAG1_3_3v:
case CURRENT_LIMIT_FLAG1_1_5v:
ra_gpio_pin_write(sc, POWER_EN_EXCARD1_3_3v, 0);
- ra_gpio_pin_write(sc, POWER_EN_EXCARD1_1_5v, 0);
+ ra_gpio_pin_write(sc, POWER_EN_EXCARD1_1_5v, 0);
KNOTE(&knotes, CURRENT_LIMIT_EVT);
cpusb_overcurrent_occurred(debounce_pin[pin]);
printf("\nExpressCard current limit received!\n");
@@ -1167,9 +1350,21 @@ ra_gpio_debounce_setup(ra_gpio_softc_t *
* interrupt sources across all three interrupt
* registers.
*/
- for (int i=0; i < __arraycount(debounce_pin); i++) {
+ for (int i = 0; i < __arraycount(debounce_pin); i++) {
u_int32_t *intr_status;
int offset;
+#if defined(MT7628)
+ if (debounce_pin[i] < 32) {
+ intr_status = &sc->sc_intr_status00_31;
+ offset = 0;
+ } else if (debounce_pin[i] < 64) {
+ intr_status = &sc->sc_intr_status32_63;
+ offset = 32;
+ } else {
+ intr_status = &sc->sc_intr_status64_95;
+ offset = 64;
+ }
+#else /* !MT7628 */
if (debounce_pin[i] < 24) {
intr_status = &sc->sc_intr_status00_23;
offset = 0;
@@ -1183,18 +1378,19 @@ ra_gpio_debounce_setup(ra_gpio_softc_t *
intr_status = &sc->sc_intr_status72_95;
offset = 72;
}
+#endif /* !MT7628 */
if (*intr_status & (1 << (debounce_pin[i] - offset))) {
pin = debounce_pin[i];
#ifdef ENABLE_RALINK_DEBUG_INFO
if (ra_gpio_pin_read(sc, pin)) {
RALINK_DEBUG(RALINK_DEBUG_INFO,
- "%s() button 0x%x, pin %d released\n",
- __func__, *intr_status, pin);
+ "%s() button 0x%x, pin %d released\n",
+ __func__, *intr_status, pin);
} else {
RALINK_DEBUG(RALINK_DEBUG_INFO,
- "%s() button 0x%x, pin %d pressed\n",
- __func__, *intr_status, pin);
+ "%s() button 0x%x, pin %d pressed\n",
+ __func__, *intr_status, pin);
}
#endif
@@ -1265,8 +1461,8 @@ enable_gpio_interrupt(ra_gpio_softc_t *s
return;
const pin_tab_t * const ptp = &pin_tab[index];
- const uint32_t mask_bit = 1 << (pin - ptp->pin_mask_base);
- const uint32_t reg_bit = 1 << (pin - ptp->pin_reg_base);
+ const uint32_t mask_bit = 1 << (pin - ptp->pin_mask_base);
+ const uint32_t reg_bit = 1 << (pin - ptp->pin_reg_base);
uint32_t r;
if (ptp->pin_rise.mask & mask_bit) {
@@ -1291,10 +1487,17 @@ enable_gpio_interrupt(ra_gpio_softc_t *s
static void
ra_gpio_softintr(void *arg)
{
+#if defined(MT7628)
RALINK_DEBUG(RALINK_DEBUG_INFO,
- "gpio softintr called with 0x%x, 0x%x, 0x%x, 0x%x\n",
- sc->sc_intr_status00_23, sc->sc_intr_status24_39,
- sc->sc_intr_status40_51, sc->sc_intr_status72_95);
+ "gpio softintr called with 0x%x, 0x%x, 0x%x\n",
+ sc->sc_intr_status00_31, sc->sc_intr_status32_63,
+ sc->sc_intr_status64_95);
+#else
+ RALINK_DEBUG(RALINK_DEBUG_INFO,
+ "gpio softintr called with 0x%x, 0x%x, 0x%x, 0x%x\n",
+ sc->sc_intr_status00_23, sc->sc_intr_status24_39,
+ sc->sc_intr_status40_51, sc->sc_intr_status72_95);
+#endif
}
/*
@@ -1310,7 +1513,7 @@ gpio_event_app_user_attach(struct knote
return 0;
}
- kn->kn_flags |= EV_CLEAR; /* automatically set */
+ kn->kn_flags |= EV_CLEAR; /* automatically set */
SLIST_INSERT_HEAD(&knotes, kn, kn_selnext);
return 0;
@@ -1336,7 +1539,8 @@ gpio_event_app_user_detach(struct knote
static int
gpio_event_app_user_event(struct knote *kn, long hint)
{
- RALINK_DEBUG_0(RALINK_DEBUG_INFO, "%s() %p hint: %ld\n", __func__, kn, hint);
+ RALINK_DEBUG_0(RALINK_DEBUG_INFO, "%s() %p hint: %ld\n",
+ __func__, kn, hint);
if (NULL == kn) {
RALINK_DEBUG(RALINK_DEBUG_ERROR, "Null kn found\n");
@@ -1373,12 +1577,12 @@ ra_gpio_toggle_LED(void *arg)
#if 0
/* Disable lit LED */
gp_write(sc, SET_SS_LED_REG,
- (1 << (led_array1[led_index++] - SS_OFFSET)));
+ (1 << (led_array1[led_index++] - SS_OFFSET)));
#endif
if (led_index == (sizeof(led_array1))) {
led_index = 0;
- for (int i=0; i < sizeof(led_array1); i++) {
+ for (int i = 0; i < sizeof(led_array1); i++) {
ra_gpio_pin_write(sc, led_array1[i], 1);
}
}
@@ -1398,7 +1602,7 @@ ra_gpio_toggle_LED(void *arg)
(led_timing_hack < 6)) {
led_timing_hack++;
callout_reset(&led_tick_callout, MS_TO_HZ(BOOT_LED_TIMING),
- ra_gpio_toggle_LED, sc);
+ ra_gpio_toggle_LED, sc);
}
#endif
}
Index: src/sys/arch/mips/ralink/ralink_gpio.h
diff -u src/sys/arch/mips/ralink/ralink_gpio.h:1.2 src/sys/arch/mips/ralink/ralink_gpio.h:1.3
--- src/sys/arch/mips/ralink/ralink_gpio.h:1.2 Thu Jul 28 15:38:49 2011
+++ src/sys/arch/mips/ralink/ralink_gpio.h Wed Oct 5 15:54:58 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: ralink_gpio.h,v 1.2 2011/07/28 15:38:49 matt Exp $ */
+/* $NetBSD: ralink_gpio.h,v 1.3 2016/10/05 15:54:58 ryo Exp $ */
/*-
* Copyright (c) 2011 CradlePoint Technology, Inc.
* All rights reserved.
@@ -43,7 +43,7 @@
#define GPIO_TR_PIN_MASK 0x017f81
#define GPIO_TR_OUTPUT_PIN_MASK 0x003b80
#define GPIO_TR_INT_PIN_MASK 0x014401
-#define GPIO_TR_INT_FEDGE_PIN_MASK 0x014401
+#define GPIO_TR_INT_FEDGE_PIN_MASK 0x014401
#define GPIO_TR_POL_MASK 0x000000
/*
@@ -148,10 +148,10 @@
#define P3_HARDWARE
#if defined(P3_HARDWARE)
#define GPIO_PB500_PIN_MASK_24_51 0x03cafe00
-#define GPIO_PB500_OUTPUT_PIN_MASK_24_51 0x03c8fe00
+#define GPIO_PB500_OUTPUT_PIN_MASK_24_51 0x03c8fe00
#else
#define GPIO_PB500_PIN_MASK_24_51 0x0fff0000
-#define GPIO_PB500_OUTPUT_PIN_MASK_24_51 0x0ffd0000
+#define GPIO_PB500_OUTPUT_PIN_MASK_24_51 0x0ffd0000
#endif
#define GPIO_PB500_INT_PIN_MASK_24_51 0x00020000 /* rising edge ints */
#define GPIO_PB500_INT_FEDGE_PIN_MASK_24_51 0x00020000
@@ -242,14 +242,14 @@
#define GPIO_SR_POL_MASK 0x000002
/* Enable RGMII */
-#define GPIO_SR_PIN_MASK_24_51 0x0000387f
-#define GPIO_SR_OUTPUT_PIN_MASK_24_51 0x0000387b
+#define GPIO_SR_PIN_MASK_24_51 0x0000387f
+#define GPIO_SR_OUTPUT_PIN_MASK_24_51 0x0000387b
#define GPIO_SR_INT_PIN_MASK_24_51 0x0004
#define GPIO_SR_INT_FEDGE_PIN_MASK_24_51 0x0004
#define GPIO_SR_POL_MASK_24_51 0x00000000
-#define GPIO_SR_PIN_MASK_72_95 0x00000fff
-#define GPIO_SR_OUTPUT_PIN_MASK_72_95 0x00000ff7
+#define GPIO_SR_PIN_MASK_72_95 0x00000fff
+#define GPIO_SR_OUTPUT_PIN_MASK_72_95 0x00000ff7
#define GPIO_SR_INT_PIN_MASK_72_95 0x0008
#define GPIO_SR_INT_FEDGE_PIN_MASK_72_95 0x0008
#define GPIO_SR_POL_MASK_72_95 0x00000000
@@ -306,7 +306,7 @@
/* Debounced Pins:
* WPS_BUTTON, SOFT_RST_IN_BUTTON, SS_BUTTON
- * CURRENT_LIMIT_FLAG USB * 3 + EXP * 2
+ * CURRENT_LIMIT_FLAG USB * 3 + EXP * 2
*/
#define DEBOUNCED_PINS 9
Index: src/sys/arch/mips/ralink/ralink_reg.h
diff -u src/sys/arch/mips/ralink/ralink_reg.h:1.8 src/sys/arch/mips/ralink/ralink_reg.h:1.9
--- src/sys/arch/mips/ralink/ralink_reg.h:1.8 Wed Oct 5 15:39:31 2016
+++ src/sys/arch/mips/ralink/ralink_reg.h Wed Oct 5 15:54:58 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: ralink_reg.h,v 1.8 2016/10/05 15:39:31 ryo Exp $ */
+/* $NetBSD: ralink_reg.h,v 1.9 2016/10/05 15:54:58 ryo Exp $ */
/*-
* Copyright (c) 2011 CradlePoint Technology, Inc.
* All rights reserved.
@@ -55,7 +55,7 @@
#endif
#define RA_BUS_FREQ 166000000 /* DDR speed */
#define RA_UART_FREQ 40000000
-#elif defined(MT7620)
+#elif defined(MT7620) || defined(MT7628)
#define RA_CLOCK_RATE 580000000
#define RA_BUS_FREQ (RA_CLOCK_RATE / 3)
#define RA_UART_FREQ 40000000
@@ -78,7 +78,9 @@
#if defined(RT3052) || defined(RT3050)
#define RA_PCM_BASE 0x10000400
#endif
+#if !defined(MT7628)
#define RA_UART_BASE 0x10000500
+#endif
#define RA_PIO_BASE 0x10000600
#if defined(RT3052) || defined(RT3050)
#define RA_GDMA_BASE 0x10000700
@@ -90,6 +92,11 @@
#define RA_I2S_BASE 0x10000A00
#define RA_SPI_BASE 0x10000B00
#define RA_UART_LITE_BASE 0x10000C00
+#if defined(MT7628)
+#define RA_UART1_BASE 0x10000D00
+#define RA_UART2_BASE 0x10000E00
+#endif
+#define RA_UART_SIZE 0x00000100
#if defined(RT3883)
#define RA_PCM_BASE 0x10002000
#define RA_GDMA_BASE 0x10002800
@@ -99,9 +106,9 @@
#define RA_FRAME_ENGINE_BASE 0x10100000
#define RA_ETH_SW_BASE 0x10110000
#define RA_ROM_BASE 0x10118000
-#if defined(RT3883) || defined(MT7620)
+#if defined(RT3883) || defined(MT7620) || defined(MT7628)
#define RA_USB_DEVICE_BASE 0x10120000
-#if defined(MT7620)
+#if defined(MT7620) || defined(MT7628)
#define RA_SDHC_BASE 0x10130000
#endif
#define RA_PCI_BASE 0x10140000
@@ -109,7 +116,7 @@
#endif
#define RA_11N_MAC_BASE 0x10180000
#define RA_USB_OTG_BASE 0x101C0000
-#if defined(RT3883) || defined(MT7620)
+#if defined(RT3883) || defined(MT7620) || defined(MT7628)
#define RA_USB_HOST_BASE 0x101C0000
#define RA_USB_BLOCK_SIZE 0x1000
#define RA_USB_EHCI_BASE (RA_USB_HOST_BASE + 0x0000)
@@ -118,7 +125,7 @@
#if defined(RT3052) || defined(RT3050)
#define RA_FLASH_BASE 0x1F000000
#define RA_FLASH_END 0x1F7FFFFF
-#elif defined(RT3883) || defined(MT7620)
+#elif defined(RT3883) || defined(MT7620) || defined(MT7628)
#define RA_FLASH_BASE 0x1C000000
#define RA_FLASH_END 0x1DFFFFFF
#endif
@@ -141,7 +148,14 @@
#define RA_SYSCTL_CLKCFG1 0x30
#define RA_SYSCTL_RST 0x34
#define RA_SYSCTL_RSTSTAT 0x38
+
+#if defined(MT7628)
+#define RA_SYSCTL_GPIO1MODE 0x60
+#define RA_SYSCTL_GPIOMODE RA_SYSCTL_GPIO1MODE
+#define RA_SYSCTL_GPIO2MODE 0x64
+#else
#define RA_SYSCTL_GPIOMODE 0x60
+#endif
#if defined(RT3050) || defined(RT3052)
#define SYSCTL_CFG0_INIC_EE_SDRAM __BIT(29)
@@ -172,6 +186,16 @@
#define SYSCTL_CFG0_XTAL_FREQ_SEL __BIT(6)
#define SYSCTL_CFG0_DRAM_TYPE __BITS(5,4)
#define SYSCTL_CFG0_CHIP_MODE __BITS(3,0)
+#elif defined(MT7628)
+#define SYSCTL_CFG0_TEST_CODE __BITS(31,24)
+#define SYSCTL_CFG0_BS_SHADOW __BITS(20,12)
+#define SYSCTL_CFG0_DBG_JTAG_MODE __BIT(8)
+#define SYSCTL_CFG0_TEST_MODE_1 __BIT(7)
+#define SYSCTL_CFG0_XTAL_FREQ_SEL __BIT(6)
+#define SYSCTL_CFG0_EXT_BG __BIT(5)
+#define SYSCTL_CFG0_TEST_MODE_0 __BIT(4)
+#define SYSCTL_CFG0_CHIP_MODE __BITS(3,1)
+#define SYSCTL_CFG0_DRAM_TYPE __BIT(0)
#endif
#if defined(RT3883) || defined(MT7620)
@@ -188,7 +212,7 @@
#define SYSCTL_CFG1_PCI_66M_MODE __BIT(6)
#endif
-#if defined(RT3883) || defined(MT7620)
+#if defined(RT3883) || defined(MT7620) || defined(MT7628)
#define SYSCTL_CLKCFG0_REFCLK0_RATE __BITS(11,9)
#endif
#if defined(RT3883)
@@ -197,46 +221,61 @@
#define SYSCTL_CLKCFG0_REFCLK0_IS_OUT __BIT(8)
#define SYSCTL_CLKCFG0_CPU_FREQ_ADJ __BITS(3,0)
#endif
-#if defined(MT7620)
+#if defined(MT7620) || defined(MT7628)
#define SYSCTL_CLKCFG0_OSC_1US_DIV_7620 __BITS(29,24)
#define SYSCTL_CLKCFG0_INT_CLK_FDIV __BITS(22,18)
#define SYSCTL_CLKCFG0_INT_CLK_FFRAC __BITS(16,12)
#define SYSCTL_CLKCFG0_PERI_CLK_SEL __BIT(4)
+#endif
+#if defined(MT7620)
#define SYSCTL_CLKCFG0_EPHY_USE_25M __BIT(3)
#endif
#if defined(RT3883)
-#define SYSCTL_CLKCFG1_PBUS_DIV2 __BIT(30)
-#define SYSCTL_CLKCFG1_SYS_TCK_EN __BIT(29)
-#define SYSCTL_CLKCFG1_FE_GDMA_PCLK_EN __BIT(22)
-#define SYSCTL_CLKCFG1_PCIE_CLK_EN_3883 __BIT(21)
-#define SYSCTL_CLKCFG1_UPHY1_CLK_EN __BIT(20)
-#define SYSCTL_CLKCFG1_PCI_CLK_EN __BIT(19)
-#define SYSCTL_CLKCFG1_UPHY0_CLK_EN_3883 __BIT(18)
-#define SYSCTL_CLKCFG1_GE2_CLK_EN_3883 __BIT(17)
-#define SYSCTL_CLKCFG1_GE1_CLK_EN_3883 __BIT(16)
+#define SYSCTL_CLKCFG1_PBUS_DIV2 __BIT(30)
+#define SYSCTL_CLKCFG1_SYS_TCK_EN __BIT(29)
+#define SYSCTL_CLKCFG1_FE_GDMA_PCLK_EN __BIT(22)
+#define SYSCTL_CLKCFG1_PCIE_CLK_EN_3883 __BIT(21)
+#define SYSCTL_CLKCFG1_UPHY1_CLK_EN __BIT(20)
+#define SYSCTL_CLKCFG1_PCI_CLK_EN __BIT(19)
+#define SYSCTL_CLKCFG1_UPHY0_CLK_EN_3883 __BIT(18)
+#define SYSCTL_CLKCFG1_GE2_CLK_EN_3883 __BIT(17)
+#define SYSCTL_CLKCFG1_GE1_CLK_EN_3883 __BIT(16)
+#endif
+#if defined(MT7628)
+#define SYSCTL_CLKCFG1_PWM_CLK_EN_7628 __BIT(31)
+#define SYSCTL_CLKCFG1_AUX_SYS_TCK_EN_7628 __BIT(29)
+#define SYSCTL_CLKCFG1_MIPSC_CLK_EN_7628 __BIT(28)
+#define SYSCTL_CLKCFG1_UPHY0_CLK_EN_7628 __BIT(22)
+#define SYSCTL_CLKCFG1_UART2_CLK_EN_7628 __BIT(20)
+#define SYSCTL_CLKCFG1_UART1_CLK_EN_7628 __BIT(19)
+#define SYSCTL_CLKCFG1_UART0_CLK_EN_7628 __BIT(12)
#endif
#if defined(MT7620)
-#define SYSCTL_CLKCFG1_SDHC_CLK_EN __BIT(30)
-#define SYSCTL_CLKCFG1_AUX_SYS_TCK_EN __BIT(28)
-#define SYSCTL_CLKCFG1_PCIE_CLK_EN_7620 __BIT(26)
-#define SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620 __BIT(25)
-#define SYSCTL_CLKCFG1_ESW_CLK_EN __BIT(23)
-#define SYSCTL_CLKCFG1_FE_CLK_EN __BIT(21)
-#define SYSCTL_CLKCFG1_UARTL_CLK_EN __BIT(19)
-#define SYSCTL_CLKCFG1_SPI_CLK_EN __BIT(18)
-#define SYSCTL_CLKCFG1_I2S_CLK_EN __BIT(17)
-#define SYSCTL_CLKCFG1_I2C_CLK_EN __BIT(16)
-#define SYSCTL_CLKCFG1_NAND_CLK_EN __BIT(15)
-#define SYSCTL_CLKCFG1_GDMA_CLK_EN __BIT(14)
-#define SYSCTL_CLKCFG1_GPIO_CLK_EN __BIT(13)
-#define SYSCTL_CLKCFG1_UART_CLK_EN __BIT(12)
-#define SYSCTL_CLKCFG1_PCM_CLK_EN __BIT(11)
-#define SYSCTL_CLKCFG1_MC_CLK_EN __BIT(10)
-#define SYSCTL_CLKCFG1_INTC_CLK_EN __BIT(9)
-#define SYSCTL_CLKCFG1_TIMER_CLK_EN __BIT(8)
-#define SYSCTL_CLKCFG1_GE2_CLK_EN_7620 __BIT(7)
-#define SYSCTL_CLKCFG1_GE1_CLK_EN_7620 __BIT(6)
+#define SYSCTL_CLKCFG1_AUX_SYS_TCK_EN __BIT(28)
+#define SYSCTL_CLKCFG1_FE_CLK_EN __BIT(21)
+#define SYSCTL_CLKCFG1_UARTL_CLK_EN __BIT(19)
+#define SYSCTL_CLKCFG1_GE2_CLK_EN_7620 __BIT(7)
+#define SYSCTL_CLKCFG1_GE1_CLK_EN_7620 __BIT(6)
+#define SYSCTL_CLKCFG1_GE2_CLK_EN_7620 __BIT(7)
+#define SYSCTL_CLKCFG1_GE1_CLK_EN_7620 __BIT(6)
+#endif
+#if defined(MT7620) || defined(MT7628)
+#define SYSCTL_CLKCFG1_SDHC_CLK_EN __BIT(30)
+#define SYSCTL_CLKCFG1_PCIE_CLK_EN_7620 __BIT(26)
+#define SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620 __BIT(25)
+#define SYSCTL_CLKCFG1_ESW_CLK_EN __BIT(23)
+#define SYSCTL_CLKCFG1_SPI_CLK_EN __BIT(18)
+#define SYSCTL_CLKCFG1_I2S_CLK_EN __BIT(17)
+#define SYSCTL_CLKCFG1_I2C_CLK_EN __BIT(16)
+#define SYSCTL_CLKCFG1_NAND_CLK_EN __BIT(15)
+#define SYSCTL_CLKCFG1_GDMA_CLK_EN __BIT(14)
+#define SYSCTL_CLKCFG1_GPIO_CLK_EN __BIT(13)
+#define SYSCTL_CLKCFG1_UART_CLK_EN __BIT(12)
+#define SYSCTL_CLKCFG1_PCM_CLK_EN __BIT(11)
+#define SYSCTL_CLKCFG1_MC_CLK_EN __BIT(10)
+#define SYSCTL_CLKCFG1_INTC_CLK_EN __BIT(9)
+#define SYSCTL_CLKCFG1_TIMER_CLK_EN __BIT(8)
#endif
#if defined(RT3883) || defined(MT7620)
@@ -248,73 +287,113 @@
#define RA_SYSCTL_MEMO1 0x6C
#endif
-#define RST_PPE_7620 __BIT(31)
-#define RST_SDHC_7620 __BIT(30)
-#define RST_MIPS_CNT_7620 __BIT(28)
-#define RST_PCIPCIE_3883 __BIT(27)
-#define RST_FLASH_3883 __BIT(26)
-#define RST_PCIE0_7620 __BIT(26)
-#define RST_UDEV_3883 __BIT(25)
-#define RST_UHST0_7620 __BIT(25)
-#define RST_PCI_3883 __BIT(24)
-#define RST_EPHY_7620 __BIT(24)
-#define RST_PCIE_3883 __BIT(23)
-#define RST_ESW_7620 __BIT(23)
-#define RST_UHST __BIT(22)
-#define RST_FE __BIT(21)
-#define RST_WLAN __BIT(20)
-#define RST_UARTL __BIT(19)
-#define RST_SPI __BIT(18)
-#define RST_I2S __BIT(17)
-#define RST_I2C __BIT(16)
-#define RST_NAND __BIT(15)
-#define RST_DMA __BIT(14)
-#define RST_PIO __BIT(13)
-#define RST_UART __BIT(12)
-#define RST_PCM __BIT(11)
-#define RST_MC __BIT(10)
-#define RST_INTC __BIT(9)
-#define RST_TIMER __BIT(8)
-#define RST_GE2 __BIT(7)
-#define RST_GE1 __BIT(6)
-#define RST_SYS __BIT(0)
-
-#define GPIOMODE_RGMII __BIT(9)
-#define GPIOMODE_SDRAM __BIT(8)
-#define GPIOMODE_MDIO __BIT(7)
-#define GPIOMODE_JTAG __BIT(6)
-#define GPIOMODE_UARTL __BIT(5)
-#define GPIOMODE_UARTF2 __BIT(4)
-#define GPIOMODE_UARTF1 __BIT(3)
-#define GPIOMODE_UARTF0 __BIT(2)
+#define RST_PPE_7620 __BIT(31)
+#define RST_PWM_7628 __BIT(31)
+#define RST_SDHC_7620 __BIT(30)
+#define RST_CRYPTO_7628 __BIT(29)
+#define RST_MIPS_CNT_7620 __BIT(28)
+#define RST_PCIPCIE_3883 __BIT(27)
+#define RST_FLASH_3883 __BIT(26)
+#define RST_PCIE0_7620 __BIT(26)
+#define RST_UDEV_3883 __BIT(25)
+#define RST_UHST0_7620 __BIT(25)
+#define RST_PCI_3883 __BIT(24)
+#define RST_EPHY_7620 __BIT(24)
+#define RST_PCIE_3883 __BIT(23)
+#define RST_ESW_7620 __BIT(23)
+#define RST_UHST __BIT(22)
+#define RST_FE __BIT(21)
+#define RST_WLAN __BIT(20)
+#define RST_UART2_7628 __BIT(20)
+#define RST_UARTL __BIT(19)
+#define RST_UART1_7628 __BIT(19)
+#define RST_SPI __BIT(18)
+#define RST_I2S __BIT(17)
+#define RST_I2C __BIT(16)
+#define RST_NAND __BIT(15)
+#define RST_DMA __BIT(14)
+#define RST_PIO __BIT(13)
+#define RST_UART __BIT(12)
+#define RST_UART0_7628 __BIT(12)
+#define RST_PCM __BIT(11)
+#define RST_MC __BIT(10)
+#define RST_INTC __BIT(9)
+#define RST_TIMER __BIT(8)
+#define RST_GE2 __BIT(7)
+#define RST_GE1 __BIT(6)
+#define RST_HIF_7628 __BIT(5)
+#define RST_WIFI_7628 __BIT(4)
+#define RST_SPIS_7628 __BIT(3)
+#define RST_SYS __BIT(0)
+
+#if defined(MT7628)
+#define GPIO1MODE_PWM1 __BITS(31,30)
+#define GPIO1MODE_PWM0 __BITS(29,18)
+#define GPIO1MODE_UART2 __BITS(27,26)
+#define GPIO1MODE_UART1 __BITS(25,24)
+#define GPIO1MODE_I2C __BITS(21,20)
+#define GPIOMODE_I2C GPIO1MODE_I2C
+#define GPIO1MODE_REFCLK __BIT(18)
+#define GPIO1MODE_PERST __BIT(16)
+#define GPIO1MODE_ESD __BIT(15)
+#define GPIO1MODE_WDT __BIT(14)
+#define GPIO1MODE_SPI __BIT(12)
+#define GPIO1MODE_SD __BITS(11,10)
+#define GPIO1MODE_UART0 __BITS(9,8)
+#define GPIO1MODE_I2S __BITS(7,6)
+#define GPIO1MODE_SPI_CS1 __BITS(5,4)
+#define GPIO1MODE_SPIS __BITS(3,2)
+#define GPIO1MODE_GPIO __BITS(1,0)
+#define GPIO2MODE_P4_LED_KN __BITS(27,26)
+#define GPIO2MODE_P3_LED_KN __BITS(25,24)
+#define GPIO2MODE_P2_LED_KN __BITS(23,22)
+#define GPIO2MODE_P1_LED_KN __BITS(21,10)
+#define GPIO2MODE_P0_LED_KN __BITS(19,18)
+#define GPIO2MODE_WLED_KN __BITS(17,16)
+#define GPIO2MODE_P4_LED_AN __BITS(11,10)
+#define GPIO2MODE_P3_LED_AN __BITS(9,8)
+#define GPIO2MODE_P2_LED_AN __BITS(7,6)
+#define GPIO2MODE_P1_LED_AN __BITS(5,4)
+#define GPIO2MODE_P0_LED_AN __BITS(3,2)
+#define GPIO2MODE_WLED_AN __BITS(1,0)
+#else
+#define GPIOMODE_RGMII __BIT(9)
+#define GPIOMODE_SDRAM __BIT(8)
+#define GPIOMODE_MDIO __BIT(7)
+#define GPIOMODE_JTAG __BIT(6)
+#define GPIOMODE_UARTL __BIT(5)
+#define GPIOMODE_UARTF2 __BIT(4)
+#define GPIOMODE_UARTF1 __BIT(3)
+#define GPIOMODE_UARTF0 __BIT(2)
#define GPIOMODE_UARTF_0_2 \
(GPIOMODE_UARTF0|GPIOMODE_UARTF1|GPIOMODE_UARTF2)
-#define GPIOMODE_SPI __BIT(1)
-#define GPIOMODE_I2C __BIT(0)
+#define GPIOMODE_SPI __BIT(1)
+#define GPIOMODE_I2C __BIT(0)
+#endif
/*
* Timer Registers
*/
-#define RA_TIMER_STAT 0x00
-#define RA_TIMER_0_LOAD 0x10
-#define RA_TIMER_0_VALUE 0x14
-#define RA_TIMER_0_CNTRL 0x18
-#define RA_TIMER_1_LOAD 0x20
-#define RA_TIMER_1_VALUE 0x24
-#define RA_TIMER_1_CNTRL 0x28
-
-#define TIMER_1_RESET __BIT(5)
-#define TIMER_0_RESET __BIT(4)
-#define TIMER_1_INT_STATUS __BIT(1)
-#define TIMER_0_INT_STATUS __BIT(0)
-#define TIMER_TEST_EN __BIT(15)
-#define TIMER_EN __BIT(7)
-#define TIMER_MODE(x) (((x) & 0x3) << 4)
-#define TIMER_MODE_FREE 0
-#define TIMER_MODE_PERIODIC 1
-#define TIMER_MODE_TIMEOUT 2
-#define TIMER_MODE_WDOG 3 /* only valid for TIMER_1 */
-#define TIMER_PRESCALE(x) (((x) & 0xf) << 0)
+#define RA_TIMER_STAT 0x00
+#define RA_TIMER_0_LOAD 0x10
+#define RA_TIMER_0_VALUE 0x14
+#define RA_TIMER_0_CNTRL 0x18
+#define RA_TIMER_1_LOAD 0x20
+#define RA_TIMER_1_VALUE 0x24
+#define RA_TIMER_1_CNTRL 0x28
+
+#define TIMER_1_RESET __BIT(5)
+#define TIMER_0_RESET __BIT(4)
+#define TIMER_1_INT_STATUS __BIT(1)
+#define TIMER_0_INT_STATUS __BIT(0)
+#define TIMER_TEST_EN __BIT(15)
+#define TIMER_EN __BIT(7)
+#define TIMER_MODE(x) (((x) & 0x3) << 4)
+#define TIMER_MODE_FREE 0
+#define TIMER_MODE_PERIODIC 1
+#define TIMER_MODE_TIMEOUT 2
+#define TIMER_MODE_WDOG 3 /* only valid for TIMER_1 */
+#define TIMER_PRESCALE(x) (((x) & 0xf) << 0)
#define TIMER_PRESCALE_DIV_1 0
#define TIMER_PRESCALE_DIV_4 1
#define TIMER_PRESCALE_DIV_8 2
@@ -335,62 +414,131 @@
/*
* Interrupt Controller Registers
*/
+#if defined(MT7628)
+#define RA_INTCTL_IRQ0STAT 0x9c
+#define RA_INTCTL_IRQ1STAT 0xa0
+#define RA_INTCTL_TYPE 0x00
+#define RA_INTCTL_RAW 0xa4
+#define RA_INTCTL_ENABLE 0x80
+#define RA_INTCTL_DISABLE 0x78
+#else
#define RA_INTCTL_IRQ0STAT 0x00
#define RA_INTCTL_IRQ1STAT 0x04
#define RA_INTCTL_TYPE 0x20
#define RA_INTCTL_RAW 0x30
#define RA_INTCTL_ENABLE 0x34
#define RA_INTCTL_DISABLE 0x38
+#endif
+/* Interrupt controller mask bit */
+#define INT_GLOBAL 31
+#define INT_GLOBAL_EN __BIT(INT_GLOBAL)
+#if defined(MT7628)
+#define INT_WDOG 24
+#define INT_UART2 22
+#define INT_UART1 21
+#define INT_UARTL 20
+#endif
+#define INT_UDEV 19
+#define INT_USB 18
+#define INT_ETHSW 17
+#define INT_R2P 15
+#define INT_SDHC 14
+#define INT_CRYPTO 13
+#if !defined(MT7628)
+#define INT_UARTL 12
+#endif
+#define INT_SPI 11
+#define INT_I2S 10
+#define INT_PERF 9
+#define INT_NAND 8
+#define INT_DMA 7
+#define INT_PIO 6
+#define INT_UARTF 5
+#define INT_PCM 4
+#define INT_ILLACC 3
+#if !defined(MT7628)
+#define INT_WDOG 2
+#endif
+#define INT_TIMER0 1
+#define INT_SYSCTL 0
-#define INT_GLOBAL __BIT(31)
-#define INT_UDEV __BIT(19)
-#define INT_USB __BIT(18)
-#define INT_ETHSW __BIT(17)
-#define INT_R2P __BIT(15)
-#define INT_SDHC __BIT(14)
-#define INT_UARTL __BIT(12)
-#define INT_SPI __BIT(11)
-#define INT_I2S __BIT(10)
-#define INT_PERF __BIT(9)
-#define INT_NAND __BIT(8)
-#define INT_DMA __BIT(7)
-#define INT_PIO __BIT(6)
-#define INT_UARTF __BIT(5)
-#define INT_PCM __BIT(4)
-#define INT_ILLACC __BIT(3)
-#define INT_WDOG __BIT(2)
-#define INT_TIMER0 __BIT(1)
-#define INT_SYSCTL __BIT(0)
/*
* Ralink Linear CPU Interrupt Mapping For Lists
*/
-#define RA_IRQ_LOW 0
-#define RA_IRQ_HIGH 1
-#define RA_IRQ_PCI 2
-#define RA_IRQ_FENGINE 3
-#define RA_IRQ_WLAN 4
-#define RA_IRQ_TIMER 5
-#define RA_IRQ_SYSCTL 6
-#define RA_IRQ_TIMER0 7
-#define RA_IRQ_WDOG 8
-#define RA_IRQ_ILLACC 9
-#define RA_IRQ_PCM 10
-#define RA_IRQ_UARTF 11
-#define RA_IRQ_PIO 12
-#define RA_IRQ_DMA 13
-#define RA_IRQ_NAND 14
-#define RA_IRQ_PERF 15
-#define RA_IRQ_I2S 16
-#define RA_IRQ_UARTL 17
-#define RA_IRQ_ETHSW 18
-#define RA_IRQ_USB 19
-#define RA_IRQ_MAX 20
+enum ralink_irq {
+ /* CPU interrupts */
+ RA_IRQ_LOW = 0,
+ RA_IRQ_HIGH,
+ RA_IRQ_PCI,
+ RA_IRQ_FENGINE,
+ RA_IRQ_WLAN,
+ RA_IRQ_TIMER,
+
+ /* pseudo IRQ for Interrupt controller */
+ RA_IRQ_SYSCTL,
+ RA_IRQ_TIMER0,
+ RA_IRQ_WDOG,
+ RA_IRQ_ILLACC,
+ RA_IRQ_PCM,
+ RA_IRQ_UARTF,
+ RA_IRQ_PIO,
+ RA_IRQ_DMA,
+ RA_IRQ_NAND,
+ RA_IRQ_PERF,
+ RA_IRQ_I2S,
+ RA_IRQ_SPI,
+ RA_IRQ_UARTL,
+ RA_IRQ_CRYPTO,
+ RA_IRQ_SDHC,
+ RA_IRQ_R2P,
+ RA_IRQ_ETHSW,
+ RA_IRQ_USB,
+ RA_IRQ_UDEV,
+ RA_IRQ_UART1,
+ RA_IRQ_UART2,
+ RA_IRQ_MAX
+};
/*
* General Purpose I/O
*/
+#if defined(MT7628)
+#define RA_PIO_00_31_DIR 0x00
+#define RA_PIO_32_63_DIR 0x04
+#define RA_PIO_64_95_DIR 0x08
+#define RA_PIO_00_31_POLARITY 0x10
+#define RA_PIO_32_63_POLARITY 0x14
+#define RA_PIO_64_95_POLARITY 0x18
+#define RA_PIO_00_31_DATA 0x20
+#define RA_PIO_32_63_DATA 0x24
+#define RA_PIO_64_95_DATA 0x28
+#define RA_PIO_00_31_SET_BIT 0x30
+#define RA_PIO_32_63_SET_BIT 0x34
+#define RA_PIO_64_95_SET_BIT 0x38
+#define RA_PIO_00_31_CLR_BIT 0x40
+#define RA_PIO_32_63_CLR_BIT 0x44
+#define RA_PIO_64_95_CLR_BIT 0x48
+#define RA_PIO_00_31_INT_RISE_EN 0x50
+#define RA_PIO_32_63_INT_RISE_EN 0x54
+#define RA_PIO_64_95_INT_RISE_EN 0x58
+#define RA_PIO_00_31_INT_FALL_EN 0x60
+#define RA_PIO_32_63_INT_FALL_EN 0x64
+#define RA_PIO_64_95_INT_FALL_EN 0x68
+#define RA_PIO_00_31_INT_HIGH_EN 0x70
+#define RA_PIO_32_63_INT_HIGH_EN 0x74
+#define RA_PIO_64_95_INT_HIGH_EN 0x78
+#define RA_PIO_00_31_INT_LOW_EN 0x80
+#define RA_PIO_32_63_INT_LOW_EN 0x84
+#define RA_PIO_64_95_INT_LOW_EN 0x88
+#define RA_PIO_00_31_INT_STAT 0x90
+#define RA_PIO_32_63_INT_STAT 0x94
+#define RA_PIO_64_95_INT_STAT 0x98
+#define RA_PIO_00_31_INT_STAT_EDGE 0xA0
+#define RA_PIO_32_63_INT_STAT_EDGE 0xA4
+#define RA_PIO_64_95_INT_STAT_EDGE 0xA8
+#else
#define RA_PIO_00_23_INT 0x00
#define RA_PIO_00_23_EDGE_INT 0x04
#define RA_PIO_00_23_INT_RISE_EN 0x08
@@ -431,12 +579,25 @@
#define RA_PIO_72_95_SET_BIT 0xa4
#define RA_PIO_72_95_CLR_BIT 0xa8
#define RA_PIO_72_95_TGL_BIT 0xac
-
+#endif
/*
* UART registers
*/
+#if defined(MT7628)
+#define RA_UART_RBR 0x00
+#define RA_UART_TBR 0x00
+#define RA_UART_IER 0x04
+#define RA_UART_IIR 0x08
+#define RA_UART_FCR 0x08
+#define RA_UART_LCR 0x0c
+#define RA_UART_MCR 0x10
+#define RA_UART_LSR 0x14
+#define RA_UART_MSR 0x18
+#define RA_UART_DLL 0x00
+#define RA_UART_DLM 0x04
+#else
#define RA_UART_RBR 0x00
#define RA_UART_TBR 0x04
#define RA_UART_IER 0x08
@@ -447,10 +608,11 @@
#define RA_UART_LSR 0x1C
#define RA_UART_MSR 0x20
#define RA_UART_DLL 0x28
+#endif
-#define UART_IER_ELSI __BIT(2) /* Receiver Line Status Interrupt Enable */
-#define UART_IER_ETBEI __BIT(1) /* Transmit Buffer Empty Interrupt Enable */
+#define UART_IER_ELSI __BIT(2) /* RX Line Status Interrupt Enable */
+#define UART_IER_ETBEI __BIT(1) /* TX Buffer Empty Interrupt Enable */
#define UART_IER_ERBFI __BIT(0)
/* Data Ready or Character Time-Out Interrupt Enable */
@@ -461,10 +623,10 @@
#define UART_IIR_IID1 __BIT(1) /* Interrupt Source Encoded */
#define UART_IIR_IP __BIT(0) /* Interrupt Pending (active low) */
-#define UART_FCR_RXTRIG1 __BIT(7) /* Receiver Interrupt Trigger Level */
-#define UART_FCR_RXTRIG0 __BIT(6) /* Receiver Interrupt Trigger Level */
-#define UART_FCR_TXTRIG1 __BIT(5) /* Transmitter Interrupt Trigger Level */
-#define UART_FCR_TXTRIG0 __BIT(4) /* Transmitter Interrupt Trigger Level */
+#define UART_FCR_RXTRIG1 __BIT(7) /* RX Interrupt Trigger Level */
+#define UART_FCR_RXTRIG0 __BIT(6) /* RX Interrupt Trigger Level */
+#define UART_FCR_TXTRIG1 __BIT(5) /* TX Interrupt Trigger Level */
+#define UART_FCR_TXTRIG0 __BIT(4) /* TX Interrupt Trigger Level */
#define UART_FCR_DMAMODE __BIT(3) /* Enable DMA transfers */
#define UART_FCR_TXRST __BIT(2) /* Reset Transmitter FIFO */
#define UART_FCR_RXRST __BIT(1) /* Reset Receiver FIFO */
@@ -559,6 +721,71 @@
/*
* Frame Engine registers
*/
+#if defined(MT7628)
+#define RA_FE_TX_BASE_PTR_0 0x800 /* TX Ring #0 Base Pointer */
+#define RA_FE_TX_MAX_CNT_0 0x804 /* TX Ring #0 Maximum Count */
+#define RA_FE_TX_CTX_IDX_0 0x808 /* TX Ring #0 CPU pointer */
+#define RA_FE_TX_DTX_IDX_0 0x80c /* TX Ring #0 DMA poitner */
+#define RA_FE_PDMA_TX0_PTR RA_FE_TX_BASE_PTR_0
+#define RA_FE_PDMA_TX0_COUNT RA_FE_TX_MAX_CNT_0
+#define RA_FE_PDMA_TX0_CPU_IDX RA_FE_TX_CTX_IDX_0
+#define RA_FE_PDMA_TX0_DMA_IDX RA_FE_TX_DTX_IDX_0
+#define RA_FE_TX_BASE_PTR_1 0x810 /* TX Ring #1 Base Pointer */
+#define RA_FE_TX_MAX_CNT_1 0x814 /* TX Ring #1 Maximum Count */
+#define RA_FE_TX_CTX_IDX_1 0x818 /* TX Ring #1 CPU pointer */
+#define RA_FE_TX_DTX_IDX_1 0x81c /* TX Ring #1 DMA poitner */
+#define RA_FE_TX_BASE_PTR_2 0x820 /* TX Ring #2 Base Pointer */
+#define RA_FE_TX_MAX_CNT_2 0x824 /* TX Ring #2 Maximum Count */
+#define RA_FE_TX_CTX_IDX_2 0x828 /* TX Ring #2 CPU pointer */
+#define RA_FE_TX_DTX_IDX_2 0x82c /* TX Ring #2 DMA poitner */
+#define RA_FE_TX_BASE_PTR_3 0x830 /* TX Ring #3 Base Pointer */
+#define RA_FE_TX_MAX_CNT_3 0x834 /* TX Ring #3 Maximum Count */
+#define RA_FE_TX_CTX_IDX_3 0x838 /* TX Ring #3 CPU pointer */
+#define RA_FE_TX_DTX_IDX_3 0x83c /* TX Ring #3 DMA poitner */
+#define RA_FE_RX_BASE_PTR_0 0x900 /* RX Ring #0 Base Pointer */
+#define RA_FE_RX_MAX_CNT_0 0x904 /* RX Ring #0 Maximum Count */
+#define RA_FE_RX_CRX_IDX_0 0x908 /* RX Ring #0 CPU pointer */
+#define RA_FE_RX_DRX_IDX_0 0x90c /* RX Ring #0 DMA poitner */
+#define RA_FE_PDMA_RX0_PTR RA_FE_RX_BASE_PTR_0
+#define RA_FE_PDMA_RX0_COUNT RA_FE_RX_MAX_CNT_0
+#define RA_FE_PDMA_RX0_CPU_IDX RA_FE_RX_CRX_IDX_0
+#define RA_FE_PDMA_RX0_DMA_IDX RA_FE_RX_DRX_IDX_0
+#define RA_FE_RX_BASE_PTR_1 0x910 /* RX Ring #1 Base Pointer */
+#define RA_FE_RX_MAX_CNT_1 0x914 /* RX Ring #1 Maximum Count */
+#define RA_FE_RX_CRX_IDX_1 0x918 /* RX Ring #1 CPU pointer */
+#define RA_FE_RX_DRX_IDX_1 0x91c /* RX Ring #1 DMA poitner */
+#define RA_FE_PDMA_INFO 0xa00 /* PDMA Information */
+#define RA_FE_PDMA_GLOBAL_CFG 0xa04 /* PDMA Global Configuration */
+#define RA_FE_DELAY_INT_CFG 0xa0c /* Delay Interrupt Configuration */
+#define RA_FE_FREEQ_THRES 0xa10 /* Free Queue Threshold */
+#define RA_FE_INT_STATUS 0xa20 /* Interrupt Status */
+#define RA_FE_INT_MASK 0xa28 /* Interrupt Mask */
+#define RA_FE_INT_RX_COHERENT __BIT(31)
+#define RA_FE_INT_RX_DLY __BIT(30)
+#define RA_FE_INT_TX_COHERENT __BIT(29)
+#define RA_FE_INT_TX_DLY_INT __BIT(28)
+#define RA_FE_INT_RX_DONE_INT1 __BIT(17)
+#define RA_FE_INT_RX_DONE_INT0 __BIT(16)
+#define RA_FE_INT_TX_DONE_INT3 __BIT(3)
+#define RA_FE_INT_TX_DONE_INT2 __BIT(2)
+#define RA_FE_INT_TX_DONE_INT1 __BIT(1)
+#define RA_FE_INT_TX_DONE_INT0 __BIT(0)
+
+#define RA_FE_PDMA_SCH 0xa80 /* Scheduler Configuration for Q0&Q1 */
+#define RA_FE_PDMA_WRR 0xa84 /* Scheduler Configuration for Q2&Q3 */
+#define RA_FE_SDM_CON 0xc00 /* Switch DMA Control */
+#define RA_FE_SDM_RING 0xc04 /* Switch DMA Rx Ring */
+#define RA_FE_SDM_TRING 0xc08 /* Switch DMA TX Ring */
+#define RA_FE_SDM_MAC_ADRL 0xc0c /* Switch MAC Address LSB */
+#define RA_FE_SDM_MAC_ADRH 0xc10 /* Switch MAC Address MSB */
+#define RA_FE_GDMA1_MAC_LSB RA_FE_SDM_MAC_ADRL
+#define RA_FE_GDMA1_MAC_MSB RA_FE_SDM_MAC_ADRH
+#define RA_FE_SDM_TPCNT 0xd00 /* Switch DMA Tx Packet Count */
+#define RA_FE_SDM_TBCNT 0xd04 /* Switch DMA TX Byte Count */
+#define RA_FE_SDM_RPCNT 0xd08 /* Switch DMA RX Packet Count */
+#define RA_FE_SDM_RBCNT 0xd0c /* Switch DMA RX Byte Count */
+#define RA_FE_SDM_CS_ERR 0xd10 /* Switch DMA RX Checksum Error */
+#else /* !MT7628 */
#define RA_FE_MDIO_ACCESS 0x000
#define RA_FE_MDIO_CFG1 0x004
#define RA_FE_GLOBAL_CFG 0x008
@@ -628,6 +855,7 @@
#define RA_FE_PDMA_TX3_CPU_IDX 0x158
#define RA_FE_PDMA_TX3_DMA_IDX 0x15C
#define RA_FE_PDMA_FC_CFG 0x1F0
+#endif /* !MT7628 */
/* TODO: FE_COUNTERS */
#define MDIO_ACCESS_TRG __BIT(31)
@@ -729,11 +957,15 @@
/*
* 10/100 Switch registers
*/
-
#define RA_ETH_SW_ISR 0x00
#define RA_ETH_SW_IMR 0x04
#define RA_ETH_SW_FCT0 0x08
+#define RA_ETH_SW_FCT0_FC_RLS_TH(x) (((x) & 0xff) << 24)
+#define RA_ETH_SW_FCT0_FC_SET_TH(x) (((x) & 0xff) << 16)
+#define RA_ETH_SW_FCT0_DROP_RLS_TH(x) (((x) & 0xff) << 8)
+#define RA_ETH_SW_FCT0_DROP_SET_TH(x) (((x) & 0xff) << 0)
#define RA_ETH_SW_FCT1 0x0C
+#define RA_ETH_SW_FCT1_PORT_TH(x) (((x) & 0xff) << 0)
#define RA_ETH_SW_PFC0 0x10
#define RA_ETH_SW_PFC1 0x14
#define RA_ETH_SW_PFC2 0x18
@@ -778,8 +1010,8 @@
#define RA_ETH_SW_LEDP4 0xB4
#define RA_ETH_SW_WDOG 0xB8
#define RA_ETH_SW_DBG 0xBC
-#define RA_ETH_SW_PCTL0 0xC0
-#define RA_ETH_SW_PCTL1 0xC4
+#define RA_ETH_SW_PCTL0 0xC0 /* PCR0 */
+#define RA_ETH_SW_PCTL1 0xC4 /* PCR1 */
#define RA_ETH_SW_FPORT 0xC8
#define RA_ETH_SW_FTC2 0xCC
#define RA_ETH_SW_QSS0 0xD0
@@ -1107,8 +1339,8 @@
#define PCICFG_P2P_BR_DEVNUM0 __BITS(19,16)
#define PCICFG_PSIRST __BIT(1)
#define RA_PCI_PCIINT 0x0008
-#define PCIINT_INT3 __BIT(21) // PCIe1 interrupt
-#define PCIINT_INT2 __BIT(20) // PCIe0 interrupt
+#define PCIINT_INT3 __BIT(21) /* PCIe1 interrupt */
+#define PCIINT_INT2 __BIT(20) /* PCIe0 interrupt */
#define PCIINT_INT1 __BIT(19)
#define PCIINT_INT0 __BIT(18)
#define RA_PCI_PCIENA 0x000c
Index: src/sys/arch/mips/ralink/ralink_var.h
diff -u src/sys/arch/mips/ralink/ralink_var.h:1.6 src/sys/arch/mips/ralink/ralink_var.h:1.7
--- src/sys/arch/mips/ralink/ralink_var.h:1.6 Wed Apr 30 00:51:01 2014
+++ src/sys/arch/mips/ralink/ralink_var.h Wed Oct 5 15:54:58 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: ralink_var.h,v 1.6 2014/04/30 00:51:01 matt Exp $ */
+/* $NetBSD: ralink_var.h,v 1.7 2016/10/05 15:54:58 ryo Exp $ */
/*-
* Copyright (c) 2011 CradlePoint Technology, Inc.
* All rights reserved.
@@ -49,6 +49,7 @@ struct mainbus_attach_args {
const char *ma_name;
bus_space_tag_t ma_memt;
bus_dma_tag_t ma_dmat;
+ bus_addr_t ma_addr;
};
#define SERIAL_CONSOLE 1
Added files:
Index: src/sys/arch/evbmips/conf/LINKITSMART7688
diff -u /dev/null src/sys/arch/evbmips/conf/LINKITSMART7688:1.1
--- /dev/null Wed Oct 5 15:54:58 2016
+++ src/sys/arch/evbmips/conf/LINKITSMART7688 Wed Oct 5 15:54:58 2016
@@ -0,0 +1,286 @@
+# $NetBSD: LINKITSMART7688,v 1.1 2016/10/05 15:54:58 ryo Exp $
+#
+# MediaTek MT7688
+#
+
+include "arch/evbmips/conf/std.rasoc"
+
+makeoptions COPY_SYMTAB=1 # size for embedded symbol table
+
+options RALINK_CONSOLE_EARLY
+options RALINK_CONADDR=RA_UART2_BASE
+
+options MT7628
+options CONSPEED=57600
+
+maxusers 8
+
+# Size reduction options
+#options VNODE_OP_NOINLINE
+#options PIPE_SOCKETPAIR # smaller, but slower pipe(2)
+#options SOSEND_NO_LOAN
+
+# Standard system options
+
+options INSECURE # disable kernel security levels - X needs this
+
+options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
+options NTP # NTP phase/frequency locked loop
+
+options KTRACE # system call tracing via ktrace(1)
+
+#options SYSVMSG # System V-like message queues
+#options SYSVSEM # System V-like semaphores
+#options SYSVSHM # System V-like memory sharing
+#options SHMMAXPGS=2048 # 2048 pages is the default
+
+#options NMBCLUSTERS=1024
+#options MCLSHIFT=12 # 4k mbuf clusters (increases pool max's to 4k as well)
+
+#options USERCONF # userconf(4) support
+#options SYSCTL_INCLUDE_DESCR # Include sysctl descriptions in kernel
+
+# Diagnostic/debugging support options
+options DIAGNOSTIC # expensive kernel consistency checks
+#options LOCKDEBUG
+#options KSTACK_CHECK_MAGIC
+#options DEBUG # expensive debugging checks/support
+options DDB # in-kernel debugger
+options DDB_ONPANIC=1 # see also sysctl(7): `ddb.onpanic'
+#options DDB_HISTORY_SIZE=512 # enable history editing in DDB
+#options DDB_COMMANDONENTER="w/b 0x90000128 0 ; bt" # disable watchdog & drop history on enter
+#options KGDB # remote debugger
+#options KGDB_DEVNAME="\"com\"",KGDB_DEVADDR=0x2f8,KGDB_DEVRATE=9600
+#makeoptions DEBUG="-g2" # compile full symbol table
+#makeoptions COPTS="-Os" # Optimise for space.
+
+#makeoptions PROF="-p" # build profiling in
+#options GPROF
+
+# Compatibility options
+#options COMPAT_NOMID # NetBSD 0.8, 386BSD, and BSDI
+#options COMPAT_09 # NetBSD 0.9,
+#options COMPAT_10 # NetBSD 1.0,
+#options COMPAT_11 # NetBSD 1.1,
+#options COMPAT_12 # NetBSD 1.2 (and 386BSD and BSDI),
+#options COMPAT_13 # NetBSD 1.3 (and 386BSD and BSDI),
+#options COMPAT_14 # NetBSD 1.4,
+#options COMPAT_15 # NetBSD 1.5,
+#options COMPAT_16 # NetBSD 1.6,
+#options COMPAT_20 # NetBSD 2.0,
+#options COMPAT_30 # NetBSD 3.0,
+#options COMPAT_40 # NetBSD 4.0,
+options COMPAT_50 # NetBSD 5.0,
+options COMPAT_60 # NetBSD 6.0, and
+options COMPAT_70 # NetBSD 7.0 binary compatibility.
+#options COMPAT_43 # 4.3BSD, 386BSD, and BSDI
+#options COMPAT_386BSD_MBRPART # recognize old partition ID
+#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
+
+#options COMPAT_SVR4 # binary compatibility with SVR4
+#options COMPAT_IBCS2 # binary compatibility with SCO and ISC
+#options COMPAT_LINUX # binary compatibility with Linux
+#options COMPAT_FREEBSD # binary compatibility with FreeBSD
+#options COMPAT_BSDPTY # /dev/[pt]ty?? ptys.
+
+# File systems
+file-system FFS # UFS
+file-system EXT2FS # second extended file system (linux)
+#file-system LFS # log-structured file system
+file-system MFS # memory file system
+file-system NFS # Network File System client
+#file-system CD9660 # ISO 9660 + Rock Ridge file system
+file-system MSDOSFS # MS-DOS file system
+#file-system FDESC # /dev/fd
+file-system KERNFS # /kern
+#file-system NULLFS # loopback file system
+#file-system PORTAL # portal filesystem (still experimental)
+file-system PROCFS # /proc
+#file-system UMAPFS # NULLFS + uid and gid remapping
+#file-system UNION # union file system
+#file-system SMBFS # experimental - CIFS; also needs nsmb (below)
+file-system PTYFS # /dev/pts/N support
+file-system TMPFS # Efficient memory file-system
+
+# File system options
+#options QUOTA # UFS quotas
+#options FFS_EI # FFS Endian Independant support
+#options NFSSERVER # Network File System server
+options FFS_NO_SNAPSHOT # No FF snapshot support
+#options EXT2FS_SYSTEM_FLAGS # makes ext2fs file flags (append and immutable) behave as system flags.
+
+# Networking options
+#options GATEWAY # packet forwarding
+options INET # IP + ICMP + TCP + UDP
+options MROUTING # IP multicast routing
+options INET6 # IPV6
+#options IPSEC # IP security
+#options IPSEC_DEBUG # debug for IP security
+#options PIM # Protocol Independent Multicast
+#options NETATALK # AppleTalk networking protocols
+#options PPP_BSDCOMP # BSD-Compress compression support for PPP
+#options PPP_DEFLATE # Deflate compression support for PPP
+#options PPP_FILTER # Active filter support for PPP (requires bpf)
+#options IPFILTER_LOG # ipmon(8) log support
+#options IPFILTER_LOOKUP # ippool(8) support
+#options IPFILTER_DEFAULT_BLOCK # block all packets by default
+#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
+
+#options ALTQ # Manipulate network interfaces' output queues
+#options ALTQ_BLUE # Stochastic Fair Blue
+#options ALTQ_CBQ # Class-Based Queueing
+#options ALTQ_CDNR # Diffserv Traffic Conditioner
+#options ALTQ_FIFOQ # First-In First-Out Queue
+#options ALTQ_FLOWVALVE # RED/flow-valve (red-penalty-box)
+#options ALTQ_HFSC # Hierarchical Fair Service Curve
+#options ALTQ_LOCALQ # Local queueing discipline
+#options ALTQ_PRIQ # Priority Queueing
+#options ALTQ_RED # Random Early Detection
+#options ALTQ_RIO # RED with IN/OUT
+#options ALTQ_WFQ # Weighted Fair Queueing
+
+# JIT compiler for bpfilter
+#options SLJIT
+#options BPFJIT
+
+# These options enable verbose messages for several subsystems.
+# Warning, these may compile large string tables into the kernel!
+#options EISAVERBOSE # verbose EISA device autoconfig messages
+#options PCIVERBOSE # verbose PCI device autoconfig messages
+#options PCI_CONFIG_DUMP # verbosely dump PCI config space
+#options PCMCIAVERBOSE # verbose PCMCIA configuration messages
+#options SCSIVERBOSE # human readable SCSI error messages
+options USBVERBOSE # verbose USB device autoconfig messages
+
+# Options for necessary to use MD
+#options MEMORY_DISK_HOOKS
+#options MEMORY_DISK_IS_ROOT # force root on memory disk
+#options MEMORY_DISK_SERVER=0 # no userspace memory disk support
+#options MEMORY_DISK_ROOT_SIZE=8192 # embed the FS into the system for now
+#options MEMORY_RBFLAGS=0 # keep the kernel from forcing single user mode
+
+# Options for NFS root boot
+#options NFS_BOOT_DHCP,NFS_BOOT_BOOTPARAM,NFS_BOOT_BOOTSTATIC
+options NFS_BOOT_BOOTSTATIC
+options NFS_BOOTSTATIC_MYIP="\"192.168.0.1\""
+options NFS_BOOTSTATIC_GWIP="\"192.168.0.1\""
+options NFS_BOOTSTATIC_MASK="\"255.255.255.0\""
+options NFS_BOOTSTATIC_SERVADDR="\"192.168.0.5\""
+options NFS_BOOTSTATIC_SERVER="\"192.168.0.5:server:/path/to/root\""
+
+# Need more mbufs for IPsec VPN
+#options NMBCLUSTERS=4096
+
+# LinkItSmart7688 dev board root on embedded NFS mount disk
+#config netbsd root on ? type ?
+#config netbsd root on sd0a type ffs dumps none
+config netbsd root on reth0 type nfs dumps none
+
+mainbus0 at root
+cpu0 at mainbus?
+
+# UARTs
+com0 at mainbus? addr 0x10000c00
+com1 at mainbus? addr 0x10000d00
+com2 at mainbus? addr 0x10000e00
+
+# Watchdog
+rwdog0 at mainbus?
+options RA_WDOG_DEFAULT_PERIOD=10
+#options RA_WDOG_DEFAULT_MODE=WDOG_MODE_DISARMED
+options RA_WDOG_DEFAULT_MODE=WDOG_MODE_KTICKLE
+
+# Ethernet MACs
+reth* at mainbus?
+options RALINK_ETH_MACADDR="00:00:aa:bb:cc:dd" # according to u-boot env
+
+# MII/PHY support
+ukphy* at mii? phy ? # generic unknown PHYs
+
+# PCI/PCIe support
+rpci0 at mainbus?
+pci* at rpci?
+
+# GPIO support
+rgpio0 at mainbus?
+gpio* at rgpio?
+
+# I2C support
+ri2c0 at mainbus?
+iic* at ri2c?
+
+# NOR Flash
+#options NOR_VERBOSE
+#cfi0 at mainbus0
+#nor0 at cfi0
+#flash0 at nor0 offset 0x00000000 size 0x00030000 # u-boot
+#flash1 at nor0 offset 0x00030000 size 0x00010000 # u-boot env
+#flash2 at nor0 offset 0x00040000 size 0x00010000 # factory
+#flash3 at nor0 offset 0x00050000 size 0x007b0000 # firmware
+
+# USB support on rusb0
+ehci* at mainbus?
+usb* at ehci?
+
+# USB support on rusb0
+ohci* at mainbus?
+usb* at ohci?
+
+# USB device drivers
+include "dev/usb/usbdevices.config"
+
+midi* at midibus?
+
+
+# Pseudo-Devices
+
+pseudo-device crypto # /dev/crypto device
+pseudo-device swcrypto # software crypto implementation
+
+# disk/mass storage pseudo-devices
+#pseudo-device md # memory disk device (ramdisk)
+#options MEMORY_DISK_HOOKS # enable root ramdisk
+#options MEMORY_DISK_DYNAMIC # loaded via kernel module(7)
+
+#pseudo-device vnd # disk-like interface to files
+#options VND_COMPRESSION # compressed vnd(4)
+
+# network pseudo-devices
+pseudo-device bpfilter # Berkeley packet filter
+#pseudo-device carp # Common Address Redundancy Protocol
+pseudo-device ipfilter # IP filter (firewall) and NAT
+pseudo-device loop # network loopback
+#pseudo-device mpls # MPLS pseudo-interface
+pseudo-device ppp # Point-to-Point Protocol
+pseudo-device pppoe # PPP over Ethernet (RFC 2516)
+#options PPPOE_SERVER # Enable PPPoE server via link0
+pseudo-device sl # Serial Line IP
+pseudo-device strip # Starmode Radio IP (Metricom)
+pseudo-device irframetty # IrDA frame line discipline
+pseudo-device tap # virtual Ethernet
+pseudo-device tun # network tunneling over tty
+pseudo-device gre # generic L3 over IP tunnel
+pseudo-device gif # IPv[46] over IPv[46] tunnel (RFC 1933)
+#pseudo-device faith # IPv[46] TCP relay translation i/f
+pseudo-device stf # 6to4 IPv6 over IPv4 encapsulation
+pseudo-device vlan # IEEE 802.1q encapsulation
+pseudo-device bridge # simple inter-network bridging
+#options BRIDGE_IPF # bridge uses IP/IPv6 pfil hooks too
+pseudo-device agr # IEEE 802.3ad link aggregation
+#pseudo-device pf # PF packet filter
+#pseudo-device pflog # PF log if
+#pseudo-device pfsync # PF sync if
+#pseudo-device npf # NPF packet filter
+#pseudo-device etherip # Tunnel Ethernet over IP
+# srt is EXPERIMENTAL
+#pseudo-device srt # source-address-based routing
+
+# miscellaneous pseudo-devices
+pseudo-device pty # pseudo-terminals
+pseudo-device sequencer # MIDI sequencer
+pseudo-device clockctl # user control of clock subsystem
+pseudo-device ksyms # /dev/ksyms
+pseudo-device lockstat # lock profiling
+pseudo-device bcsp # BlueCore Serial Protocol
+pseudo-device btuart # Bluetooth HCI UART (H4)
+#pseudo-device gpiosim 1 # GPIO simulator
