CVS commit: src/sys/arch/mips/mips

[Michael Lorenz]

Module Name:    src
Committed By:   macallan
Date:           Sat Oct  8 00:39:53 UTC 2016

Modified Files:
        src/sys/arch/mips/mips: cache_r5k.c

Log Message:
- don't clear KX when disabling interrupts
- sign extend addresses as needed
- use PAGE_SIZE instead of blindly assuming 4KB
now n32 kernels work again on my R5k SGIs
thanks to skrll@ for helping me with this


To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/mips/mips/cache_r5k.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/arch/mips/mips/cache_r5k.c
diff -u src/sys/arch/mips/mips/cache_r5k.c:1.16 src/sys/arch/mips/mips/cache_r5k.c:1.17
--- src/sys/arch/mips/mips/cache_r5k.c:1.16	Mon Jul 11 16:15:36 2016
+++ src/sys/arch/mips/mips/cache_r5k.c	Sat Oct  8 00:39:53 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: cache_r5k.c,v 1.16 2016/07/11 16:15:36 matt Exp $	*/
+/*	$NetBSD: cache_r5k.c,v 1.17 2016/10/08 00:39:53 macallan Exp $	*/
 
 /*
  * Copyright 2001 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache_r5k.c,v 1.16 2016/07/11 16:15:36 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache_r5k.c,v 1.17 2016/10/08 00:39:53 macallan Exp $");
 
 #include <sys/param.h>
 
@@ -428,11 +428,11 @@ r5k_sdcache_wbinv_range_index(vaddr_t va
 	 * address out of them.
 	 */
 	va = MIPS_PHYS_TO_KSEG0(va & (mips_cache_info.mci_sdcache_size - 1));
-	r5k_sdcache_wbinv_range(va, size);
+	r5k_sdcache_wbinv_range((intptr_t)va, size);
 }
 
-#define	mips_r5k_round_page(x)	round_line(x, 128 * 32)
-#define	mips_r5k_trunc_page(x)	trunc_line(x, 128 * 32)
+#define	mips_r5k_round_page(x)	round_line(x, PAGE_SIZE)
+#define	mips_r5k_trunc_page(x)	trunc_line(x, PAGE_SIZE)
 
 void
 r5k_sdcache_wbinv_range(register_t va, vsize_t size)
@@ -442,14 +442,8 @@ r5k_sdcache_wbinv_range(register_t va, v
 
 	va = mips_r5k_trunc_page(va);
 
-	__asm volatile(
-		".set noreorder		\n\t"
-		".set noat		\n\t"
-		"mfc0 %0, $12		\n\t"
-		"mtc0 $0, $12		\n\t"
-		".set reorder		\n\t"
-		".set at"
-		: "=r"(ostatus));
+	ostatus = mips_cp0_status_read();
+	mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE);
 
 	__asm volatile("mfc0 %0, $28" : "=r"(taglo));
 	__asm volatile("mtc0 $0, $28");
@@ -458,6 +452,6 @@ r5k_sdcache_wbinv_range(register_t va, v
 		cache_op_r4k_line(va, CACHEOP_R4K_HIT_WB_INV|CACHE_R4K_SD);
 	}
 
-	__asm volatile("mtc0 %0, $12; nop" :: "r"(ostatus));
+	mips_cp0_status_write(ostatus);
 	__asm volatile("mtc0 %0, $28; nop" :: "r"(taglo));
 }