Module Name: src
Committed By: jmcneill
Date: Sun Oct 8 18:00:36 UTC 2017
Modified Files:
src/sys/arch/arm/sunxi: files.sunxi sunxi_gpio.c sunxi_gpio.h
sunxi_mmc.c sunxi_platform.c sunxi_platform.h
Added Files:
src/sys/arch/arm/sunxi: sun9i_a80_ccu.c sun9i_a80_ccu.h
sun9i_a80_gpio.c sun9i_a80_mmcclk.c
Log Message:
Add Allwinner A80 (sun9i) support.
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/sunxi/files.sunxi
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/sunxi/sun9i_a80_ccu.c \
src/sys/arch/arm/sunxi/sun9i_a80_ccu.h \
src/sys/arch/arm/sunxi/sun9i_a80_gpio.c \
src/sys/arch/arm/sunxi/sun9i_a80_mmcclk.c
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/sunxi/sunxi_gpio.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/sunxi/sunxi_gpio.h
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/sunxi/sunxi_mmc.c \
src/sys/arch/arm/sunxi/sunxi_platform.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/sunxi/sunxi_platform.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/sunxi/files.sunxi
diff -u src/sys/arch/arm/sunxi/files.sunxi:1.31 src/sys/arch/arm/sunxi/files.sunxi:1.32
--- src/sys/arch/arm/sunxi/files.sunxi:1.31 Sat Oct 7 21:53:16 2017
+++ src/sys/arch/arm/sunxi/files.sunxi Sun Oct 8 18:00:36 2017
@@ -1,4 +1,4 @@
-# $NetBSD: files.sunxi,v 1.31 2017/10/07 21:53:16 jmcneill Exp $
+# $NetBSD: files.sunxi,v 1.32 2017/10/08 18:00:36 jmcneill Exp $
#
# Configuration info for Allwinner sunxi family SoCs
#
@@ -58,6 +58,11 @@ device sun8ih3rccu: sunxi_ccu
attach sun8ih3rccu at fdt with sunxi_h3_r_ccu
file arch/arm/sunxi/sun8i_h3_r_ccu.c sunxi_h3_r_ccu
+# CCU (A80)
+device sun9ia80ccu: sunxi_ccu
+attach sun9ia80ccu at fdt with sunxi_a80_ccu
+file arch/arm/sunxi/sun9i_a80_ccu.c sunxi_a80_ccu
+
# CCU (A64)
device sun50ia64ccu: sunxi_ccu
attach sun50ia64ccu at fdt with sunxi_a64_ccu
@@ -78,6 +83,11 @@ device sunxigmacclk
attach sunxigmacclk at fdt with sunxi_gmacclk
file arch/arm/sunxi/sunxi_gmacclk.c sunxi_gmacclk
+# SD/MMC-COMM (A80)
+device sun9immcclk
+attach sun9immcclk at fdt with sunxi_a80_mmcclk
+file arch/arm/sunxi/sun9i_a80_mmcclk.c sunxi_a80_mmcclk
+
# Interrupt controller
device sunxiintc: pic, pic_splfuncs
attach sunxiintc at fdt with sunxi_intc
@@ -93,6 +103,7 @@ file arch/arm/sunxi/sun6i_a31_gpio.c su
file arch/arm/sunxi/sun7i_a20_gpio.c sunxi_gpio & soc_sun7i_a20
file arch/arm/sunxi/sun8i_a83t_gpio.c sunxi_gpio & soc_sun8i_a83t
file arch/arm/sunxi/sun8i_h3_gpio.c sunxi_gpio & soc_sun8i_h3
+file arch/arm/sunxi/sun9i_a80_gpio.c sunxi_gpio & soc_sun9i_a80
file arch/arm/sunxi/sun50i_a64_gpio.c sunxi_gpio & soc_sun50i_a64
# UART
@@ -213,5 +224,7 @@ defflag opt_soc.h SOC_SUN7I_A20: SOC_S
defflag opt_soc.h SOC_SUN8I: SOC_SUNXI
defflag opt_soc.h SOC_SUN8I_A83T: SOC_SUN8I
defflag opt_soc.h SOC_SUN8I_H3: SOC_SUN8I
+defflag opt_soc.h SOC_SUN9I: SOC_SUNXI
+defflag opt_soc.h SOC_SUN9I_A80: SOC_SUN9I
defflag opt_soc.h SOC_SUN50I: SOC_SUNXI
defflag opt_soc.h SOC_SUN50I_A64: SOC_SUN50I
Index: src/sys/arch/arm/sunxi/sunxi_gpio.c
diff -u src/sys/arch/arm/sunxi/sunxi_gpio.c:1.14 src/sys/arch/arm/sunxi/sunxi_gpio.c:1.15
--- src/sys/arch/arm/sunxi/sunxi_gpio.c:1.14 Fri Oct 6 21:20:59 2017
+++ src/sys/arch/arm/sunxi/sunxi_gpio.c Sun Oct 8 18:00:36 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_gpio.c,v 1.14 2017/10/06 21:20:59 jmcneill Exp $ */
+/* $NetBSD: sunxi_gpio.c,v 1.15 2017/10/08 18:00:36 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -29,7 +29,7 @@
#include "opt_soc.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_gpio.c,v 1.14 2017/10/06 21:20:59 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_gpio.c,v 1.15 2017/10/08 18:00:36 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -47,6 +47,7 @@ __KERNEL_RCSID(0, "$NetBSD: sunxi_gpio.c
#include <arm/sunxi/sunxi_gpio.h>
+#define SUNXI_GPIO_MAX_EINT_BANK 5
#define SUNXI_GPIO_MAX_EINT 32
#define SUNXI_GPIO_PORT(port) (0x24 * (port))
@@ -60,15 +61,15 @@ __KERNEL_RCSID(0, "$NetBSD: sunxi_gpio.c
#define SUNXI_GPIO_PULL_UP 1
#define SUNXI_GPIO_PULL_DOWN 2
#define SUNXI_GPIO_PULL_PINMASK(pin) (0x3 << (((pin) % 16) * 2))
-#define SUNXI_GPIO_INT_CFG(eint) (0x200 + (0x4 * ((eint) / 8)))
+#define SUNXI_GPIO_INT_CFG(bank, eint) (0x200 + (0x20 * (bank)) + (0x4 * ((eint) / 8)))
#define SUNXI_GPIO_INT_MODEMASK(eint) (0xf << (((eint) % 8) * 4))
#define SUNXI_GPIO_INT_MODE_POS_EDGE 0x0
#define SUNXI_GPIO_INT_MODE_NEG_EDGE 0x1
#define SUNXI_GPIO_INT_MODE_HIGH_LEVEL 0x2
#define SUNXI_GPIO_INT_MODE_LOW_LEVEL 0x3
#define SUNXI_GPIO_INT_MODE_DOUBLE_EDGE 0x4
-#define SUNXI_GPIO_INT_CTL 0x210
-#define SUNXI_GPIO_INT_STATUS 0x214
+#define SUNXI_GPIO_INT_CTL(bank) (0x210 + 0x20 * (bank))
+#define SUNXI_GPIO_INT_STATUS(bank) (0x214 + 0x20 * (bank))
static const struct of_compat_data compat_data[] = {
#ifdef SOC_SUN4I_A10
@@ -92,6 +93,10 @@ static const struct of_compat_data compa
{ "allwinner,sun8i-h3-pinctrl", (uintptr_t)&sun8i_h3_padconf },
{ "allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&sun8i_h3_r_padconf },
#endif
+#ifdef SOC_SUN9I_A80
+ { "allwinner,sun9i-a80-pinctrl", (uintptr_t)&sun9i_a80_padconf },
+ { "allwinner,sun9i-a80-r-pinctrl", (uintptr_t)&sun9i_a80_r_padconf },
+#endif
#ifdef SOC_SUN50I_A64
{ "allwinner,sun50i-a64-pinctrl", (uintptr_t)&sun50i_a64_padconf },
{ "allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&sun50i_a64_r_padconf },
@@ -103,6 +108,7 @@ struct sunxi_gpio_eint {
int (*eint_func)(void *);
void *eint_arg;
int eint_flags;
+ int eint_bank;
int eint_num;
};
@@ -117,8 +123,10 @@ struct sunxi_gpio_softc {
gpio_pin_t *sc_pins;
device_t sc_gpiodev;
+ u_int sc_eint_bank_max;
+
void *sc_ih;
- struct sunxi_gpio_eint sc_eint[SUNXI_GPIO_MAX_EINT];
+ struct sunxi_gpio_eint sc_eint[SUNXI_GPIO_MAX_EINT_BANK][SUNXI_GPIO_MAX_EINT];
};
struct sunxi_gpio_pin {
@@ -388,22 +396,27 @@ sunxi_gpio_intr(void *priv)
struct sunxi_gpio_softc * const sc = priv;
struct sunxi_gpio_eint *eint;
uint32_t status, bit;
+ u_int bank;
int ret = 0;
- status = GPIO_READ(sc, SUNXI_GPIO_INT_STATUS);
- GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS, status);
-
- while ((bit = ffs32(status)) != 0) {
- status &= ~__BIT(bit - 1);
- eint = &sc->sc_eint[bit - 1];
- if (eint->eint_func == NULL)
+ for (bank = 0; bank <= sc->sc_eint_bank_max; bank++) {
+ status = GPIO_READ(sc, SUNXI_GPIO_INT_STATUS(bank));
+ if (status == 0)
continue;
- const bool mpsafe = (eint->eint_flags & FDT_INTR_MPSAFE) != 0;
- if (!mpsafe)
- KERNEL_LOCK(1, curlwp);
- ret |= eint->eint_func(eint->eint_arg);
- if (!mpsafe)
- KERNEL_UNLOCK_ONE(curlwp);
+ GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(bank), status);
+
+ while ((bit = ffs32(status)) != 0) {
+ status &= ~__BIT(bit - 1);
+ eint = &sc->sc_eint[bank][bit - 1];
+ if (eint->eint_func == NULL)
+ continue;
+ const bool mpsafe = (eint->eint_flags & FDT_INTR_MPSAFE) != 0;
+ if (!mpsafe)
+ KERNEL_LOCK(1, curlwp);
+ ret |= eint->eint_func(eint->eint_arg);
+ if (!mpsafe)
+ KERNEL_UNLOCK_ONE(curlwp);
+ }
}
return ret;
@@ -465,7 +478,7 @@ sunxi_gpio_establish(device_t dev, u_int
mutex_enter(&sc->sc_lock);
- eint = &sc->sc_eint[pin_def->eint_num];
+ eint = &sc->sc_eint[pin_def->eint_bank][pin_def->eint_num];
if (eint->eint_func != NULL) {
mutex_exit(&sc->sc_lock);
return NULL; /* in use */
@@ -480,18 +493,19 @@ sunxi_gpio_establish(device_t dev, u_int
eint->eint_func = func;
eint->eint_arg = arg;
eint->eint_flags = flags;
+ eint->eint_bank = pin_def->eint_bank;
eint->eint_num = pin_def->eint_num;
/* Configure eint mode */
- val = GPIO_READ(sc, SUNXI_GPIO_INT_CFG(eint->eint_num));
+ val = GPIO_READ(sc, SUNXI_GPIO_INT_CFG(eint->eint_bank, eint->eint_num));
val &= ~SUNXI_GPIO_INT_MODEMASK(eint->eint_num);
val |= __SHIFTIN(mode, SUNXI_GPIO_INT_MODEMASK(eint->eint_num));
- GPIO_WRITE(sc, SUNXI_GPIO_INT_CFG(eint->eint_num), val);
+ GPIO_WRITE(sc, SUNXI_GPIO_INT_CFG(eint->eint_bank, eint->eint_num), val);
/* Enable eint */
- val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL);
+ val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank));
val |= __BIT(eint->eint_num);
- GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL, val);
+ GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank), val);
mutex_exit(&sc->sc_lock);
@@ -510,10 +524,10 @@ sunxi_gpio_disestablish(device_t dev, vo
mutex_enter(&sc->sc_lock);
/* Disable eint */
- val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL);
+ val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank));
val &= ~__BIT(eint->eint_num);
- GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL, val);
- GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS, __BIT(eint->eint_num));
+ GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank), val);
+ GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(eint->eint_bank), __BIT(eint->eint_num));
eint->eint_func = NULL;
eint->eint_arg = NULL;
@@ -833,8 +847,17 @@ sunxi_gpio_attach(device_t parent, devic
sunxi_gpio_attach_ports(sc);
/* Disable all external interrupts */
- GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL, 0);
- GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS, GPIO_READ(sc, SUNXI_GPIO_INT_STATUS));
+ for (int i = 0; i < sc->sc_padconf->npins; i++) {
+ const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[i];
+ if (pin_def->eint_func == 0)
+ continue;
+ GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(pin_def->eint_bank), __BIT(pin_def->eint_num));
+ GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(pin_def->eint_bank), __BIT(pin_def->eint_num));
+
+ if (sc->sc_eint_bank_max < pin_def->eint_bank)
+ sc->sc_eint_bank_max = pin_def->eint_bank;
+ }
+ KASSERT(sc->sc_eint_bank_max < SUNXI_GPIO_MAX_EINT_BANK);
if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
aprint_error_dev(self, "failed to decode interrupt\n");
Index: src/sys/arch/arm/sunxi/sunxi_gpio.h
diff -u src/sys/arch/arm/sunxi/sunxi_gpio.h:1.6 src/sys/arch/arm/sunxi/sunxi_gpio.h:1.7
--- src/sys/arch/arm/sunxi/sunxi_gpio.h:1.6 Fri Oct 6 21:20:59 2017
+++ src/sys/arch/arm/sunxi/sunxi_gpio.h Sun Oct 8 18:00:36 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_gpio.h,v 1.6 2017/10/06 21:20:59 jmcneill Exp $ */
+/* $NetBSD: sunxi_gpio.h,v 1.7 2017/10/08 18:00:36 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -43,6 +43,7 @@ struct sunxi_gpio_pins {
const char *functions[SUNXI_GPIO_MAXFUNC];
uint8_t eint_func;
uint8_t eint_num;
+ uint8_t eint_bank;
};
struct sunxi_gpio_padconf {
@@ -77,6 +78,11 @@ extern const struct sunxi_gpio_padconf s
extern const struct sunxi_gpio_padconf sun8i_h3_r_padconf;
#endif
+#ifdef SOC_SUN9I_A80
+extern const struct sunxi_gpio_padconf sun9i_a80_padconf;
+extern const struct sunxi_gpio_padconf sun9i_a80_r_padconf;
+#endif
+
#ifdef SOC_SUN50I_A64
extern const struct sunxi_gpio_padconf sun50i_a64_padconf;
extern const struct sunxi_gpio_padconf sun50i_a64_r_padconf;
Index: src/sys/arch/arm/sunxi/sunxi_mmc.c
diff -u src/sys/arch/arm/sunxi/sunxi_mmc.c:1.9 src/sys/arch/arm/sunxi/sunxi_mmc.c:1.10
--- src/sys/arch/arm/sunxi/sunxi_mmc.c:1.9 Sun Oct 8 13:48:40 2017
+++ src/sys/arch/arm/sunxi/sunxi_mmc.c Sun Oct 8 18:00:36 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_mmc.c,v 1.9 2017/10/08 13:48:40 jmcneill Exp $ */
+/* $NetBSD: sunxi_mmc.c,v 1.10 2017/10/08 18:00:36 jmcneill Exp $ */
/*-
* Copyright (c) 2014-2017 Jared McNeill <jmcne...@invisible.ca>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.9 2017/10/08 13:48:40 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.10 2017/10/08 18:00:36 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -58,7 +58,7 @@ struct sunxi_mmc_delay {
u_int sample_phase;
};
-static const struct sunxi_mmc_delay sunxi_mmc_delays[] = {
+static const struct sunxi_mmc_delay sun7i_mmc_delays[] = {
[SUNXI_MMC_TIMING_400K] = { 180, 180 },
[SUNXI_MMC_TIMING_25M] = { 180, 75 },
[SUNXI_MMC_TIMING_50M] = { 90, 120 },
@@ -66,6 +66,14 @@ static const struct sunxi_mmc_delay sunx
[SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 90, 180 },
};
+static const struct sunxi_mmc_delay sun9i_mmc_delays[] = {
+ [SUNXI_MMC_TIMING_400K] = { 180, 180 },
+ [SUNXI_MMC_TIMING_25M] = { 180, 75 },
+ [SUNXI_MMC_TIMING_50M] = { 150, 120 },
+ [SUNXI_MMC_TIMING_50M_DDR] = { 54, 36 },
+ [SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 72, 72 },
+};
+
#define SUNXI_MMC_NDESC 16
struct sunxi_mmc_softc;
@@ -188,7 +196,14 @@ static const struct sunxi_mmc_config sun
static const struct sunxi_mmc_config sun7i_a20_mmc_config = {
.idma_xferlen = 0x2000,
.dma_ftrglevel = 0x20070008,
- .delays = sunxi_mmc_delays,
+ .delays = sun7i_mmc_delays,
+ .flags = 0,
+};
+
+static const struct sunxi_mmc_config sun9i_a80_mmc_config = {
+ .idma_xferlen = 0x10000,
+ .dma_ftrglevel = 0x200f0010,
+ .delays = sun9i_mmc_delays,
.flags = 0,
};
@@ -205,6 +220,7 @@ static const struct of_compat_data compa
{ "allwinner,sun4i-a10-mmc", (uintptr_t)&sun4i_a10_mmc_config },
{ "allwinner,sun5i-a13-mmc", (uintptr_t)&sun5i_a13_mmc_config },
{ "allwinner,sun7i-a20-mmc", (uintptr_t)&sun7i_a20_mmc_config },
+ { "allwinner,sun9i-a80-mmc", (uintptr_t)&sun9i_a80_mmc_config },
{ "allwinner,sun50i-a64-mmc", (uintptr_t)&sun50i_a64_mmc_config },
{ NULL }
};
Index: src/sys/arch/arm/sunxi/sunxi_platform.c
diff -u src/sys/arch/arm/sunxi/sunxi_platform.c:1.9 src/sys/arch/arm/sunxi/sunxi_platform.c:1.10
--- src/sys/arch/arm/sunxi/sunxi_platform.c:1.9 Fri Oct 6 21:12:23 2017
+++ src/sys/arch/arm/sunxi/sunxi_platform.c Sun Oct 8 18:00:36 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_platform.c,v 1.9 2017/10/06 21:12:23 jmcneill Exp $ */
+/* $NetBSD: sunxi_platform.c,v 1.10 2017/10/08 18:00:36 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -31,7 +31,7 @@
#include "opt_fdt_arm.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_platform.c,v 1.9 2017/10/06 21:12:23 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_platform.c,v 1.10 2017/10/08 18:00:36 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -82,6 +82,13 @@ __KERNEL_RCSID(0, "$NetBSD: sunxi_platfo
#define SUN6I_WDT_MODE 0x18
#define SUN6I_WDT_MODE_EN __BIT(0)
+#define SUN9I_WDT_BASE 0x06000ca0
+#define SUN9I_WDT_SIZE 0x20
+#define SUN9I_WDT_CFG 0x14
+#define SUN9I_WDT_CFG_SYS __BIT(0)
+#define SUN9I_WDT_MODE 0x18
+#define SUN9I_WDT_MODE_EN __BIT(0)
+
#define DEVMAP_ALIGN(a) ((a) & ~L1_S_OFFSET)
#define DEVMAP_SIZE(s) roundup2((s), L1_S_SIZE)
@@ -216,6 +223,18 @@ sun6i_platform_reset(void)
bus_space_write_4(bst, bsh, SUN6I_WDT_MODE, SUN6I_WDT_MODE_EN);
}
+static void
+sun9i_platform_reset(void)
+{
+ bus_space_tag_t bst = &armv7_generic_bs_tag;
+ bus_space_handle_t bsh;
+
+ bus_space_map(bst, SUN9I_WDT_BASE, SUN9I_WDT_SIZE, 0, &bsh);
+
+ bus_space_write_4(bst, bsh, SUN9I_WDT_CFG, SUN9I_WDT_CFG_SYS);
+ bus_space_write_4(bst, bsh, SUN9I_WDT_MODE, SUN9I_WDT_MODE_EN);
+}
+
static const struct arm_platform sun4i_platform = {
.devmap = sunxi_platform_devmap,
.bootstrap = sunxi_platform_bootstrap,
@@ -283,6 +302,19 @@ ARM_PLATFORM(sun8i_h2plus, "allwinner,su
ARM_PLATFORM(sun8i_h3, "allwinner,sun8i-h3", &sun8i_platform);
ARM_PLATFORM(sun8i_a83t, "allwinner,sun8i-a83t", &sun8i_platform);
+static const struct arm_platform sun9i_platform = {
+ .devmap = sunxi_platform_devmap,
+ .bootstrap = sunxi_platform_bootstrap,
+ .init_attach_args = sunxi_platform_init_attach_args,
+ .early_putchar = sunxi_platform_early_putchar,
+ .device_register = sunxi_platform_device_register,
+ .reset = sun9i_platform_reset,
+ .delay = gtmr_delay,
+ .uart_freq = sunxi_platform_uart_freq,
+};
+
+ARM_PLATFORM(sun9i_a80, "allwinner,sun9i-a80", &sun9i_platform);
+
static const struct arm_platform sun50i_platform = {
.devmap = sunxi_platform_devmap,
.bootstrap = sunxi_platform_bootstrap,
Index: src/sys/arch/arm/sunxi/sunxi_platform.h
diff -u src/sys/arch/arm/sunxi/sunxi_platform.h:1.1 src/sys/arch/arm/sunxi/sunxi_platform.h:1.2
--- src/sys/arch/arm/sunxi/sunxi_platform.h:1.1 Wed Jun 28 23:51:29 2017
+++ src/sys/arch/arm/sunxi/sunxi_platform.h Sun Oct 8 18:00:36 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_platform.h,v 1.1 2017/06/28 23:51:29 jmcneill Exp $ */
+/* $NetBSD: sunxi_platform.h,v 1.2 2017/10/08 18:00:36 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -33,6 +33,6 @@
#define SUNXI_CORE_VBASE (KERNEL_VM_BASE + KERNEL_VM_SIZE)
#define SUNXI_CORE_PBASE 0x01c00000
-#define SUNXI_CORE_SIZE 0x00400000
+#define SUNXI_CORE_SIZE 0x06400000
#endif /* _ARM_SUNXI_PLATFORM_H */
Added files:
Index: src/sys/arch/arm/sunxi/sun9i_a80_ccu.c
diff -u /dev/null src/sys/arch/arm/sunxi/sun9i_a80_ccu.c:1.1
--- /dev/null Sun Oct 8 18:00:36 2017
+++ src/sys/arch/arm/sunxi/sun9i_a80_ccu.c Sun Oct 8 18:00:36 2017
@@ -0,0 +1,325 @@
+/* $NetBSD: sun9i_a80_ccu.c,v 1.1 2017/10/08 18:00:36 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: sun9i_a80_ccu.c,v 1.1 2017/10/08 18:00:36 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/sunxi/sunxi_ccu.h>
+#include <arm/sunxi/sun9i_a80_ccu.h>
+
+/* CCU */
+#define PLL_PERIPH0_CTRL_REG 0x00c
+#define PLL_PERIPH1_CTRL_REG 0x02c
+#define GTBUS_CLK_CFG_REG 0x05c
+#define AHB0_CLK_CFG_REG 0x060
+#define AHB1_CLK_CFG_REG 0x064
+#define AHB2_CLK_CFG_REG 0x068
+#define APB0_CLK_CFG_REG 0x070
+#define APB1_CLK_CFG_REG 0x074
+
+/* CCU_SCLK */
+#define SDMMC0_CLK_REG 0x410
+#define SDMMC1_CLK_REG 0x414
+#define SDMMC2_CLK_REG 0x418
+#define BUS_CLK_GATING_REG0 0x580
+#define BUS_CLK_GATING_REG1 0x584
+#define BUS_CLK_GATING_REG2 0x588
+#define BUS_CLK_GATING_REG3 0x590
+#define BUS_CLK_GATING_REG4 0x594
+#define BUS_SOFT_RST_REG0 0x5a0
+#define BUS_SOFT_RST_REG1 0x5a4
+#define BUS_SOFT_RST_REG2 0x5a8
+#define BUS_SOFT_RST_REG3 0x5b0
+#define BUS_SOFT_RST_REG4 0x5b4
+
+static int sun9i_a80_ccu_match(device_t, cfdata_t, void *);
+static void sun9i_a80_ccu_attach(device_t, device_t, void *);
+
+static const char * compatible[] = {
+ "allwinner,sun9i-a80-ccu",
+ NULL
+};
+
+CFATTACH_DECL_NEW(sunxi_a80_ccu, sizeof(struct sunxi_ccu_softc),
+ sun9i_a80_ccu_match, sun9i_a80_ccu_attach, NULL, NULL);
+
+static struct sunxi_ccu_reset sun9i_a80_ccu_resets[] = {
+ SUNXI_CCU_RESET(A80_RST_BUS_FD, BUS_SOFT_RST_REG0, 0),
+ SUNXI_CCU_RESET(A80_RST_BUS_GPU_CTRL, BUS_SOFT_RST_REG0, 3),
+ SUNXI_CCU_RESET(A80_RST_BUS_SS, BUS_SOFT_RST_REG0, 5),
+ SUNXI_CCU_RESET(A80_RST_BUS_MMC, BUS_SOFT_RST_REG0, 8),
+ SUNXI_CCU_RESET(A80_RST_BUS_NAND1, BUS_SOFT_RST_REG0, 12),
+ SUNXI_CCU_RESET(A80_RST_BUS_NAND0, BUS_SOFT_RST_REG0, 13),
+ SUNXI_CCU_RESET(A80_RST_BUS_TS, BUS_SOFT_RST_REG0, 18),
+ SUNXI_CCU_RESET(A80_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20),
+ SUNXI_CCU_RESET(A80_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21),
+ SUNXI_CCU_RESET(A80_RST_BUS_SPI2, BUS_SOFT_RST_REG0, 22),
+ SUNXI_CCU_RESET(A80_RST_BUS_SPI3, BUS_SOFT_RST_REG0, 23),
+
+ SUNXI_CCU_RESET(A80_RST_BUS_OTG_PHY, BUS_SOFT_RST_REG1, 1),
+ SUNXI_CCU_RESET(A80_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21),
+ SUNXI_CCU_RESET(A80_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22),
+ SUNXI_CCU_RESET(A80_RST_BUS_HSTIMER, BUS_SOFT_RST_REG1, 23),
+ SUNXI_CCU_RESET(A80_RST_BUS_DMA, BUS_SOFT_RST_REG1, 24),
+
+ SUNXI_CCU_RESET(A80_RST_BUS_LCD0, BUS_SOFT_RST_REG2, 0),
+ SUNXI_CCU_RESET(A80_RST_BUS_LCD1, BUS_SOFT_RST_REG2, 1),
+ SUNXI_CCU_RESET(A80_RST_BUS_CSI, BUS_SOFT_RST_REG2, 4),
+ SUNXI_CCU_RESET(A80_RST_BUS_DE, BUS_SOFT_RST_REG2, 7),
+ SUNXI_CCU_RESET(A80_RST_BUS_MP, BUS_SOFT_RST_REG2, 8),
+ SUNXI_CCU_RESET(A80_RST_BUS_GPU, BUS_SOFT_RST_REG2, 9),
+
+ SUNXI_CCU_RESET(A80_RST_BUS_LRADC, BUS_SOFT_RST_REG3, 15),
+ SUNXI_CCU_RESET(A80_RST_BUS_GPADC, BUS_SOFT_RST_REG3, 17),
+
+ SUNXI_CCU_RESET(A80_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0),
+ SUNXI_CCU_RESET(A80_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1),
+ SUNXI_CCU_RESET(A80_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2),
+ SUNXI_CCU_RESET(A80_RST_BUS_I2C3, BUS_SOFT_RST_REG4, 3),
+ SUNXI_CCU_RESET(A80_RST_BUS_I2C4, BUS_SOFT_RST_REG4, 4),
+ SUNXI_CCU_RESET(A80_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16),
+ SUNXI_CCU_RESET(A80_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17),
+ SUNXI_CCU_RESET(A80_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18),
+ SUNXI_CCU_RESET(A80_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19),
+ SUNXI_CCU_RESET(A80_RST_BUS_UART4, BUS_SOFT_RST_REG4, 20),
+ SUNXI_CCU_RESET(A80_RST_BUS_UART5, BUS_SOFT_RST_REG4, 21),
+};
+
+static const char *gtbus_parents[] = { "hosc", "pll_periph0", "pll_periph1" };
+static const char *ahb0_parents[] = { "gtbus", "pll_periph0", "pll_periph1" };
+static const char *ahb1_parents[] = { "gtbus", "pll_periph0", "pll_periph1" };
+static const char *ahb2_parents[] = { "hosc", "pll_periph0", "pll_periph1" };
+static const char *apb_parents[] = { "hosc", "pll_periph0" };
+static const char *mmc_parents[] = { "hosc", "pll_periph0" };
+
+static struct sunxi_ccu_clk sun9i_a80_ccu_clks[] = {
+ SUNXI_CCU_NKMP(A80_CLK_PLL_PERIPH0, "pll_periph0", "hosc",
+ PLL_PERIPH0_CTRL_REG, /* reg */
+ __BITS(15,8), /* n */
+ __BIT(16), /* k */
+ 0, /* m */
+ __BIT(18), /* p */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NKMP_FACTOR_N_EXACT),
+ SUNXI_CCU_NKMP(A80_CLK_PLL_PERIPH1, "pll_periph1", "hosc",
+ PLL_PERIPH1_CTRL_REG, /* reg */
+ __BITS(15,8), /* n */
+ __BIT(16), /* k */
+ 0, /* m */
+ __BIT(18), /* p */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NKMP_FACTOR_N_EXACT),
+
+ SUNXI_CCU_DIV(A80_CLK_GTBUS, "gtbus", gtbus_parents,
+ GTBUS_CLK_CFG_REG, /* reg */
+ __BITS(1,0), /* div */
+ __BITS(25,24), /* sel */
+ 0),
+
+ SUNXI_CCU_DIV(A80_CLK_AHB0, "ahb0", ahb0_parents,
+ AHB0_CLK_CFG_REG, /* reg */
+ __BITS(1,0), /* div */
+ __BITS(25,24), /* sel */
+ SUNXI_CCU_DIV_POWER_OF_TWO),
+
+ SUNXI_CCU_DIV(A80_CLK_AHB1, "ahb1", ahb1_parents,
+ AHB1_CLK_CFG_REG, /* reg */
+ __BITS(1,0), /* div */
+ __BITS(25,24), /* sel */
+ SUNXI_CCU_DIV_POWER_OF_TWO),
+
+ SUNXI_CCU_DIV(A80_CLK_AHB2, "ahb2", ahb2_parents,
+ AHB2_CLK_CFG_REG, /* reg */
+ __BITS(1,0), /* div */
+ __BITS(25,24), /* sel */
+ SUNXI_CCU_DIV_POWER_OF_TWO),
+
+ SUNXI_CCU_DIV(A80_CLK_APB0, "apb0", apb_parents,
+ APB0_CLK_CFG_REG, /* reg */
+ __BITS(1,0), /* div */
+ __BIT(24), /* sel */
+ SUNXI_CCU_DIV_POWER_OF_TWO),
+
+ SUNXI_CCU_NM(A80_CLK_APB1, "apb1", apb_parents,
+ APB1_CLK_CFG_REG, /* reg */
+ __BITS(17,16), /* n */
+ __BITS(4,0), /* m */
+ __BIT(24), /* sel */
+ 0, /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO),
+
+ SUNXI_CCU_NM(A80_CLK_MMC0, "mmc0", mmc_parents,
+ SDMMC0_CLK_REG, /* reg */
+ __BITS(17,16), /* n */
+ __BITS(3,0), /* m */
+ __BITS(27,24), /* sel */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO),
+ SUNXI_CCU_PHASE(A80_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0",
+ SDMMC0_CLK_REG, __BITS(22,20)),
+ SUNXI_CCU_PHASE(A80_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0",
+ SDMMC0_CLK_REG, __BITS(10,8)),
+ SUNXI_CCU_NM(A80_CLK_MMC1, "mmc1", mmc_parents,
+ SDMMC1_CLK_REG, /* reg */
+ __BITS(17,16), /* n */
+ __BITS(3,0), /* m */
+ __BITS(27,24), /* sel */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO),
+ SUNXI_CCU_PHASE(A80_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1",
+ SDMMC1_CLK_REG, __BITS(22,20)),
+ SUNXI_CCU_PHASE(A80_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1",
+ SDMMC1_CLK_REG, __BITS(10,8)),
+ SUNXI_CCU_NM(A80_CLK_MMC2, "mmc2", mmc_parents,
+ SDMMC2_CLK_REG, /* reg */
+ __BITS(17,16), /* n */
+ __BITS(3,0), /* m */
+ __BITS(27,24), /* sel */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO),
+ SUNXI_CCU_PHASE(A80_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2",
+ SDMMC2_CLK_REG, __BITS(22,20)),
+ SUNXI_CCU_PHASE(A80_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2",
+ SDMMC2_CLK_REG, __BITS(10,8)),
+
+ SUNXI_CCU_GATE(A80_CLK_BUS_FD, "ahb0-fd", "ahb0",
+ BUS_CLK_GATING_REG0, 0),
+ SUNXI_CCU_GATE(A80_CLK_BUS_GPU_CTRL, "ahb0-gpu-ctrl", "ahb0",
+ BUS_CLK_GATING_REG0, 3),
+ SUNXI_CCU_GATE(A80_CLK_BUS_SS, "ahb0-ss", "ahb0",
+ BUS_CLK_GATING_REG0, 5),
+ SUNXI_CCU_GATE(A80_CLK_BUS_MMC, "ahb0-mmc", "ahb0",
+ BUS_CLK_GATING_REG0, 8),
+ SUNXI_CCU_GATE(A80_CLK_BUS_NAND1, "ahb0-nand1", "ahb0",
+ BUS_CLK_GATING_REG0, 12),
+ SUNXI_CCU_GATE(A80_CLK_BUS_NAND0, "ahb0-nand0", "ahb0",
+ BUS_CLK_GATING_REG0, 13),
+ SUNXI_CCU_GATE(A80_CLK_BUS_TS, "ahb0-ts", "ahb0",
+ BUS_CLK_GATING_REG0, 18),
+ SUNXI_CCU_GATE(A80_CLK_BUS_SPI0, "ahb0-spi0", "ahb0",
+ BUS_CLK_GATING_REG0, 20),
+ SUNXI_CCU_GATE(A80_CLK_BUS_SPI1, "ahb0-spi1", "ahb0",
+ BUS_CLK_GATING_REG0, 21),
+ SUNXI_CCU_GATE(A80_CLK_BUS_SPI2, "ahb0-spi2", "ahb0",
+ BUS_CLK_GATING_REG0, 22),
+ SUNXI_CCU_GATE(A80_CLK_BUS_SPI3, "ahb0-spi3", "ahb0",
+ BUS_CLK_GATING_REG0, 23),
+
+ SUNXI_CCU_GATE(A80_CLK_BUS_USB, "ahb1-usb", "ahb1",
+ BUS_CLK_GATING_REG1, 1),
+ SUNXI_CCU_GATE(A80_CLK_BUS_MSGBOX, "ahb1-msgbox", "ahb1",
+ BUS_CLK_GATING_REG1, 21),
+ SUNXI_CCU_GATE(A80_CLK_BUS_SPINLOCK, "ahb1-spinlock", "ahb1",
+ BUS_CLK_GATING_REG1, 22),
+ SUNXI_CCU_GATE(A80_CLK_BUS_HSTIMER, "ahb1-hstimer", "ahb1",
+ BUS_CLK_GATING_REG1, 23),
+ SUNXI_CCU_GATE(A80_CLK_BUS_DMA, "ahb1-dma", "ahb1",
+ BUS_CLK_GATING_REG1, 24),
+
+ SUNXI_CCU_GATE(A80_CLK_BUS_LCD0, "ahb2-lcd0", "ahb2",
+ BUS_CLK_GATING_REG2, 0),
+ SUNXI_CCU_GATE(A80_CLK_BUS_LCD1, "ahb2-lcd1", "ahb2",
+ BUS_CLK_GATING_REG2, 1),
+ SUNXI_CCU_GATE(A80_CLK_BUS_CSI, "ahb2-csi", "ahb2",
+ BUS_CLK_GATING_REG2, 4),
+ SUNXI_CCU_GATE(A80_CLK_BUS_DE, "ahb2-de", "ahb2",
+ BUS_CLK_GATING_REG2, 7),
+ SUNXI_CCU_GATE(A80_CLK_BUS_MP, "ahb2-mp", "ahb2",
+ BUS_CLK_GATING_REG2, 8),
+
+ SUNXI_CCU_GATE(A80_CLK_BUS_PIO, "apb0-pio", "apb0",
+ BUS_CLK_GATING_REG3, 5),
+ SUNXI_CCU_GATE(A80_CLK_BUS_LRADC, "apb0-lradc", "apb0",
+ BUS_CLK_GATING_REG3, 15),
+ SUNXI_CCU_GATE(A80_CLK_BUS_GPADC, "apb0-gpadc", "apb0",
+ BUS_CLK_GATING_REG3, 17),
+
+ SUNXI_CCU_GATE(A80_CLK_BUS_I2C0, "apb1-i2c0", "apb1",
+ BUS_CLK_GATING_REG4, 0),
+ SUNXI_CCU_GATE(A80_CLK_BUS_I2C1, "apb1-i2c1", "apb1",
+ BUS_CLK_GATING_REG4, 1),
+ SUNXI_CCU_GATE(A80_CLK_BUS_I2C2, "apb1-i2c2", "apb1",
+ BUS_CLK_GATING_REG4, 2),
+ SUNXI_CCU_GATE(A80_CLK_BUS_I2C3, "apb1-i2c3", "apb1",
+ BUS_CLK_GATING_REG4, 3),
+ SUNXI_CCU_GATE(A80_CLK_BUS_I2C4, "apb1-i2c4", "apb1",
+ BUS_CLK_GATING_REG4, 4),
+ SUNXI_CCU_GATE(A80_CLK_BUS_UART0, "apb1-uart0", "apb1",
+ BUS_CLK_GATING_REG4, 16),
+ SUNXI_CCU_GATE(A80_CLK_BUS_UART1, "apb1-uart1", "apb1",
+ BUS_CLK_GATING_REG4, 17),
+ SUNXI_CCU_GATE(A80_CLK_BUS_UART2, "apb1-uart2", "apb1",
+ BUS_CLK_GATING_REG4, 18),
+ SUNXI_CCU_GATE(A80_CLK_BUS_UART3, "apb1-uart3", "apb1",
+ BUS_CLK_GATING_REG4, 19),
+ SUNXI_CCU_GATE(A80_CLK_BUS_UART4, "apb1-uart4", "apb1",
+ BUS_CLK_GATING_REG4, 20),
+ SUNXI_CCU_GATE(A80_CLK_BUS_UART5, "apb1-uart5", "apb1",
+ BUS_CLK_GATING_REG4, 21),
+};
+
+static int
+sun9i_a80_ccu_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+sun9i_a80_ccu_attach(device_t parent, device_t self, void *aux)
+{
+ struct sunxi_ccu_softc * const sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+
+ sc->sc_dev = self;
+ sc->sc_phandle = faa->faa_phandle;
+ sc->sc_bst = faa->faa_bst;
+
+ sc->sc_resets = sun9i_a80_ccu_resets;
+ sc->sc_nresets = __arraycount(sun9i_a80_ccu_resets);
+
+ sc->sc_clks = sun9i_a80_ccu_clks;
+ sc->sc_nclks = __arraycount(sun9i_a80_ccu_clks);
+
+ if (sunxi_ccu_attach(sc) != 0)
+ return;
+
+ aprint_naive("\n");
+ aprint_normal(": A80 CCU\n");
+
+ sunxi_ccu_print(sc);
+}
Index: src/sys/arch/arm/sunxi/sun9i_a80_ccu.h
diff -u /dev/null src/sys/arch/arm/sunxi/sun9i_a80_ccu.h:1.1
--- /dev/null Sun Oct 8 18:00:36 2017
+++ src/sys/arch/arm/sunxi/sun9i_a80_ccu.h Sun Oct 8 18:00:36 2017
@@ -0,0 +1,215 @@
+/* $NetBSD: sun9i_a80_ccu.h,v 1.1 2017/10/08 18:00:36 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _SUN9I_A80_CCU_H
+#define _SUN9I_A80_CCU_H
+
+#define A80_RST_BUS_FD 0
+#define A80_RST_BUS_VE 1
+#define A80_RST_BUS_GPU_CTRL 2
+#define A80_RST_BUS_SS 3
+#define A80_RST_BUS_MMC 4
+#define A80_RST_BUS_NAND0 5
+#define A80_RST_BUS_NAND1 6
+#define A80_RST_BUS_SDRAM 7
+#define A80_RST_BUS_SATA 8
+#define A80_RST_BUS_TS 9
+#define A80_RST_BUS_SPI0 10
+#define A80_RST_BUS_SPI1 11
+#define A80_RST_BUS_SPI2 12
+#define A80_RST_BUS_SPI3 13
+#define A80_RST_BUS_OTG 14
+#define A80_RST_BUS_OTG_PHY 15
+#define A80_RST_BUS_MIPI_HSI 16
+#define A80_RST_BUS_GMAC 17
+#define A80_RST_BUS_MSGBOX 18
+#define A80_RST_BUS_SPINLOCK 19
+#define A80_RST_BUS_HSTIMER 20
+#define A80_RST_BUS_DMA 21
+#define A80_RST_BUS_LCD0 22
+#define A80_RST_BUS_LCD1 23
+#define A80_RST_BUS_EDP 24
+#define A80_RST_BUS_LVDS 25
+#define A80_RST_BUS_CSI 26
+#define A80_RST_BUS_HDMI0 27
+#define A80_RST_BUS_HDMI1 28
+#define A80_RST_BUS_DE 29
+#define A80_RST_BUS_MP 30
+#define A80_RST_BUS_GPU 31
+#define A80_RST_BUS_MIPI_DSI 32
+#define A80_RST_BUS_SPDIF 33
+#define A80_RST_BUS_AC97 34
+#define A80_RST_BUS_I2S0 35
+#define A80_RST_BUS_I2S1 36
+#define A80_RST_BUS_LRADC 37
+#define A80_RST_BUS_GPADC 38
+#define A80_RST_BUS_CIR_TX 39
+#define A80_RST_BUS_I2C0 40
+#define A80_RST_BUS_I2C1 41
+#define A80_RST_BUS_I2C2 42
+#define A80_RST_BUS_I2C3 43
+#define A80_RST_BUS_I2C4 44
+#define A80_RST_BUS_UART0 45
+#define A80_RST_BUS_UART1 46
+#define A80_RST_BUS_UART2 47
+#define A80_RST_BUS_UART3 48
+#define A80_RST_BUS_UART4 49
+#define A80_RST_BUS_UART5 50
+
+#define A80_CLK_PLL_C0CPUX 0
+#define A80_CLK_PLL_C1CPUX 1
+#define A80_CLK_PLL_AUDIO 2
+#define A80_CLK_PLL_PERIPH0 3
+#define A80_CLK_PLL_VE 4
+#define A80_CLK_PLL_DDR 5
+#define A80_CLK_PLL_VIDEO0 6
+#define A80_CLK_PLL_VIDEO1 7
+#define A80_CLK_PLL_GPU 8
+#define A80_CLK_PLL_DE 9
+#define A80_CLK_PLL_ISP 10
+#define A80_CLK_PLL_PERIPH1 11
+#define A80_CLK_C0CPUX 12
+#define A80_CLK_C1CPUX 13
+#define A80_CLK_ATB0 14
+#define A80_CLK_AXI0 15
+#define A80_CLK_ATB1 16
+#define A80_CLK_AXI1 17
+#define A80_CLK_GTBUS 18
+#define A80_CLK_AHB0 19
+#define A80_CLK_AHB1 20
+#define A80_CLK_AHB2 21
+#define A80_CLK_APB0 22
+#define A80_CLK_APB1 23
+#define A80_CLK_CCI400 24
+#define A80_CLK_ATS 25
+#define A80_CLK_TRACE 26
+#define A80_CLK_OUT_A 27
+#define A80_CLK_OUT_B 28
+#define A80_CLK_NAND0_0 29
+#define A80_CLK_NAND0_1 30
+#define A80_CLK_NAND1_0 31
+#define A80_CLK_NAND1_1 32
+#define A80_CLK_MMC0 33
+#define A80_CLK_MMC0_SAMPLE 34
+#define A80_CLK_MMC0_OUTPUT 35
+#define A80_CLK_MMC1 36
+#define A80_CLK_MMC1_SAMPLE 37
+#define A80_CLK_MMC1_OUTPUT 38
+#define A80_CLK_MMC2 39
+#define A80_CLK_MMC2_SAMPLE 40
+#define A80_CLK_MMC2_OUTPUT 41
+#define A80_CLK_MMC3 42
+#define A80_CLK_MMC3_SAMPLE 43
+#define A80_CLK_MMC3_OUTPUT 44
+#define A80_CLK_TS 45
+#define A80_CLK_SS 46
+#define A80_CLK_SPI0 47
+#define A80_CLK_SPI1 48
+#define A80_CLK_SPI2 49
+#define A80_CLK_SPI3 50
+#define A80_CLK_I2S0 51
+#define A80_CLK_I2S1 52
+#define A80_CLK_SPDIF 53
+#define A80_CLK_SDRAM 54
+#define A80_CLK_DE 55
+#define A80_CLK_EDP 56
+#define A80_CLK_MP 57
+#define A80_CLK_LCD0 58
+#define A80_CLK_LCD1 59
+#define A80_CLK_MIPI_DSI0 60
+#define A80_CLK_MIPI_DSI1 61
+#define A80_CLK_HDMI 62
+#define A80_CLK_HDMI_SLOW 63
+#define A80_CLK_MIPI_CSI 64
+#define A80_CLK_CSI_ISP 65
+#define A80_CLK_CSI_MISC 66
+#define A80_CLK_CSI0_MCLK 67
+#define A80_CLK_CSI1_MCLK 68
+#define A80_CLK_FD 69
+#define A80_CLK_VE 70
+#define A80_CLK_AVS 71
+#define A80_CLK_GPU_CORE 72
+#define A80_CLK_GPU_MEMORY 73
+#define A80_CLK_GPU_AXI 74
+#define A80_CLK_SATA 75
+#define A80_CLK_AC97 76
+#define A80_CLK_MIPI_HSI 77
+#define A80_CLK_GPADC 78
+#define A80_CLK_CIR_TX 79
+#define A80_CLK_BUS_FD 80
+#define A80_CLK_BUS_VE 81
+#define A80_CLK_BUS_GPU_CTRL 82
+#define A80_CLK_BUS_SS 83
+#define A80_CLK_BUS_MMC 84
+#define A80_CLK_BUS_NAND0 85
+#define A80_CLK_BUS_NAND1 86
+#define A80_CLK_BUS_SDRAM 87
+#define A80_CLK_BUS_MIPI_HSI 88
+#define A80_CLK_BUS_SATA 89
+#define A80_CLK_BUS_TS 90
+#define A80_CLK_BUS_SPI0 91
+#define A80_CLK_BUS_SPI1 92
+#define A80_CLK_BUS_SPI2 93
+#define A80_CLK_BUS_SPI3 94
+#define A80_CLK_BUS_OTG 95
+#define A80_CLK_BUS_USB 96
+#define A80_CLK_BUS_GMAC 97
+#define A80_CLK_BUS_MSGBOX 98
+#define A80_CLK_BUS_SPINLOCK 99
+#define A80_CLK_BUS_HSTIMER 100
+#define A80_CLK_BUS_DMA 101
+#define A80_CLK_BUS_LCD0 102
+#define A80_CLK_BUS_LCD1 103
+#define A80_CLK_BUS_EDP 104
+#define A80_CLK_BUS_CSI 105
+#define A80_CLK_BUS_HDMI 106
+#define A80_CLK_BUS_DE 107
+#define A80_CLK_BUS_MP 108
+#define A80_CLK_BUS_MIPI_DSI 109
+#define A80_CLK_BUS_SPDIF 110
+#define A80_CLK_BUS_PIO 111
+#define A80_CLK_BUS_AC97 112
+#define A80_CLK_BUS_I2S0 113
+#define A80_CLK_BUS_I2S1 114
+#define A80_CLK_BUS_LRADC 115
+#define A80_CLK_BUS_GPADC 116
+#define A80_CLK_BUS_TWD 117
+#define A80_CLK_BUS_CIR_TX 118
+#define A80_CLK_BUS_I2C0 119
+#define A80_CLK_BUS_I2C1 120
+#define A80_CLK_BUS_I2C2 121
+#define A80_CLK_BUS_I2C3 122
+#define A80_CLK_BUS_I2C4 123
+#define A80_CLK_BUS_UART0 124
+#define A80_CLK_BUS_UART1 125
+#define A80_CLK_BUS_UART2 126
+#define A80_CLK_BUS_UART3 127
+#define A80_CLK_BUS_UART4 128
+#define A80_CLK_BUS_UART5 129
+
+#endif /* !_SUN9I_A80_CCU_H */
Index: src/sys/arch/arm/sunxi/sun9i_a80_gpio.c
diff -u /dev/null src/sys/arch/arm/sunxi/sun9i_a80_gpio.c:1.1
--- /dev/null Sun Oct 8 18:00:36 2017
+++ src/sys/arch/arm/sunxi/sun9i_a80_gpio.c Sun Oct 8 18:00:36 2017
@@ -0,0 +1,221 @@
+/* $NetBSD: sun9i_a80_gpio.c,v 1.1 2017/10/08 18:00:36 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: sun9i_a80_gpio.c,v 1.1 2017/10/08 18:00:36 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/types.h>
+
+#include <arm/sunxi/sunxi_gpio.h>
+
+static const struct sunxi_gpio_pins a80_pins[] = {
+ { "PA0", 0, 0, { "gpio_in", "gpio_out", "gmac", NULL, "uart1", NULL, "eint" }, 6, 0, 0 },
+ { "PA1", 0, 1, { "gpio_in", "gpio_out", "gmac", NULL, "uart1", NULL, "eint" }, 6, 1, 0 },
+ { "PA2", 0, 2, { "gpio_in", "gpio_out", "gmac", NULL, "uart1", NULL, "eint" }, 6, 2, 0 },
+ { "PA3", 0, 3, { "gpio_in", "gpio_out", "gmac", NULL, "uart1", NULL, "eint" }, 6, 3, 0 },
+ { "PA4", 0, 4, { "gpio_in", "gpio_out", "gmac", NULL, "uart1", NULL, "eint" }, 6, 4, 0 },
+ { "PA5", 0, 5, { "gpio_in", "gpio_out", "gmac", NULL, "uart1", NULL, "eint" }, 6, 5, 0 },
+ { "PA6", 0, 6, { "gpio_in", "gpio_out", "gmac", NULL, "uart1", NULL, "eint" }, 6, 6, 0 },
+ { "PA7", 0, 7, { "gpio_in", "gpio_out", "gmac", NULL, "uart1", NULL, "eint" }, 6, 7, 0 },
+ { "PA8", 0, 8, { "gpio_in", "gpio_out", "gmac", NULL, "eclk", NULL, "eint" }, 6, 8, 0 },
+ { "PA9", 0, 9, { "gpio_in", "gpio_out", "gmac", NULL, "eclk", NULL, "eint" }, 6, 9, 0 },
+ { "PA10", 0, 10, { "gpio_in", "gpio_out", "gmac", NULL, "clk_out_a", NULL, "eint" }, 6, 10, 0 },
+ { "PA11", 0, 11, { "gpio_in", "gpio_out", "gmac", NULL, "clk_out_b", NULL, "eint" }, 6, 11, 0 },
+ { "PA12", 0, 12, { "gpio_in", "gpio_out", "gmac", NULL, "pwm3", NULL, "eint" }, 6, 12, 0 },
+ { "PA13", 0, 13, { "gpio_in", "gpio_out", "gmac", NULL, "pwm3", NULL, "eint" }, 6, 13, 0 },
+ { "PA14", 0, 14, { "gpio_in", "gpio_out", "gmac", NULL, "spi1", NULL, "eint" }, 6, 14, 0 },
+ { "PA15", 0, 15, { "gpio_in", "gpio_out", "gmac", NULL, "spi1", NULL, "eint" }, 6, 15, 0 },
+ { "PA16", 0, 16, { "gpio_in", "gpio_out", "gmac", NULL, "spi1", NULL, "eint" }, 6, 16, 0 },
+ { "PA17", 0, 17, { "gpio_in", "gpio_out", "gmac", NULL, "spi1", NULL, "eint" }, 6, 17, 0 },
+
+ { "PB5", 1, 5, { "gpio_in", "gpio_out", NULL, "uart3", NULL, NULL, "eint" }, 6, 5, 1 },
+ { "PB6", 1, 6, { "gpio_in", "gpio_out", NULL, "uart3", NULL, NULL, "eint" }, 6, 6, 1 },
+ { "PB14", 1, 14, { "gpio_in", "gpio_out", NULL, "mcsi", NULL, NULL, "eint" }, 6, 14, 1 },
+ { "PB15", 1, 15, { "gpio_in", "gpio_out", NULL, "mcsi", "i2c4", NULL, "eint" }, 6, 15, 1 },
+ { "PB16", 1, 16, { "gpio_in", "gpio_out", NULL, "mcsi", "i2c4", NULL, "eint" }, 6, 16, 1 },
+
+ { "PC0", 2, 0, { "gpio_in", "gpio_out", "nand0", "spi0" } },
+ { "PC1", 2, 1, { "gpio_in", "gpio_out", "nand0", "spi0" } },
+ { "PC2", 2, 2, { "gpio_in", "gpio_out", "nand0", "spi0" } },
+ { "PC3", 2, 3, { "gpio_in", "gpio_out", "nand0" } },
+ { "PC4", 2, 4, { "gpio_in", "gpio_out", "nand0" } },
+ { "PC5", 2, 5, { "gpio_in", "gpio_out", "nand0" } },
+ { "PC6", 2, 6, { "gpio_in", "gpio_out", "nand0", "mmc2" } },
+ { "PC7", 2, 7, { "gpio_in", "gpio_out", "nand0", "mmc2" } },
+ { "PC8", 2, 8, { "gpio_in", "gpio_out", "nand0", "mmc2" } },
+ { "PC9", 2, 9, { "gpio_in", "gpio_out", "nand0", "mmc2" } },
+ { "PC10", 2, 10, { "gpio_in", "gpio_out", "nand0", "mmc2" } },
+ { "PC11", 2, 11, { "gpio_in", "gpio_out", "nand0", "mmc2" } },
+ { "PC12", 2, 12, { "gpio_in", "gpio_out", "nand0", "mmc2" } },
+ { "PC13", 2, 13, { "gpio_in", "gpio_out", "nand0", "mmc2" } },
+ { "PC14", 2, 14, { "gpio_in", "gpio_out", "nand0", "mmc2" } },
+ { "PC15", 2, 15, { "gpio_in", "gpio_out", "nand0", "mmc2" } },
+ { "PC16", 2, 16, { "gpio_in", "gpio_out", "nand0", "mmc2" } },
+ { "PC17", 2, 17, { "gpio_in", "gpio_out", "nand0", "nand0_b" } },
+ { "PC18", 2, 18, { "gpio_in", "gpio_out", "nand0", "nand0_b" } },
+ { "PC19", 2, 19, { "gpio_in", "gpio_out", NULL, "spi0" } },
+
+ { "PD0", 3, 0, { "gpio_in", "gpio_out", "lcd0", "lvds0" } },
+ { "PD1", 3, 1, { "gpio_in", "gpio_out", "lcd0", "lvds0" } },
+ { "PD2", 3, 2, { "gpio_in", "gpio_out", "lcd0", "lvds0" } },
+ { "PD3", 3, 3, { "gpio_in", "gpio_out", "lcd0", "lvds0" } },
+ { "PD4", 3, 4, { "gpio_in", "gpio_out", "lcd0", "lvds0" } },
+ { "PD5", 3, 5, { "gpio_in", "gpio_out", "lcd0", "lvds0" } },
+ { "PD6", 3, 6, { "gpio_in", "gpio_out", "lcd0", "lvds0" } },
+ { "PD7", 3, 7, { "gpio_in", "gpio_out", "lcd0", "lvds0" } },
+ { "PD8", 3, 8, { "gpio_in", "gpio_out", "lcd0", "lvds0" } },
+ { "PD9", 3, 9, { "gpio_in", "gpio_out", "lcd0", "lvds0" } },
+ { "PD10", 3, 10, { "gpio_in", "gpio_out", "lcd0", "lvds1" } },
+ { "PD11", 3, 11, { "gpio_in", "gpio_out", "lcd0", "lvds1" } },
+ { "PD12", 3, 12, { "gpio_in", "gpio_out", "lcd0", "lvds1" } },
+ { "PD13", 3, 13, { "gpio_in", "gpio_out", "lcd0", "lvds1" } },
+ { "PD14", 3, 14, { "gpio_in", "gpio_out", "lcd0", "lvds1" } },
+ { "PD15", 3, 15, { "gpio_in", "gpio_out", "lcd0", "lvds1" } },
+ { "PD16", 3, 16, { "gpio_in", "gpio_out", "lcd0", "lvds1" } },
+ { "PD17", 3, 17, { "gpio_in", "gpio_out", "lcd0", "lvds1" } },
+ { "PD18", 3, 18, { "gpio_in", "gpio_out", "lcd0", "lvds1" } },
+ { "PD19", 3, 19, { "gpio_in", "gpio_out", "lcd0", "lvds1" } },
+ { "PD20", 3, 20, { "gpio_in", "gpio_out", "lcd0" } },
+ { "PD21", 3, 21, { "gpio_in", "gpio_out", "lcd0" } },
+ { "PD22", 3, 22, { "gpio_in", "gpio_out", "lcd0" } },
+ { "PD23", 3, 23, { "gpio_in", "gpio_out", "lcd0" } },
+ { "PD24", 3, 24, { "gpio_in", "gpio_out", "lcd0" } },
+ { "PD25", 3, 25, { "gpio_in", "gpio_out", "lcd0" } },
+ { "PD26", 3, 26, { "gpio_in", "gpio_out", "lcd0" } },
+ { "PD27", 3, 27, { "gpio_in", "gpio_out", "lcd0" } },
+
+ { "PE0", 4, 0, { "gpio_in", "gpio_out", "csi", "ts", NULL, NULL, "eint" }, 6, 0, 2 },
+ { "PE1", 4, 1, { "gpio_in", "gpio_out", "csi", "ts", NULL, NULL, "eint" }, 6, 1, 2 },
+ { "PE2", 4, 2, { "gpio_in", "gpio_out", "csi", "ts", NULL, NULL, "eint" }, 6, 2, 2 },
+ { "PE3", 4, 3, { "gpio_in", "gpio_out", "csi", "ts", NULL, NULL, "eint" }, 6, 3, 2 },
+ { "PE4", 4, 4, { "gpio_in", "gpio_out", "csi", "spi2", "uart5", NULL, "eint" }, 6, 4, 2 },
+ { "PE5", 4, 5, { "gpio_in", "gpio_out", "csi", "spi2", "uart5", NULL, "eint" }, 6, 5, 2 },
+ { "PE6", 4, 6, { "gpio_in", "gpio_out", "csi", "spi2", "uart5", NULL, "eint" }, 6, 6, 2 },
+ { "PE7", 4, 7, { "gpio_in", "gpio_out", "csi", "spi2", "uart5", NULL, "eint" }, 6, 7, 2 },
+ { "PE8", 4, 8, { "gpio_in", "gpio_out", "csi", "ts", NULL, NULL, "eint" }, 6, 8, 2 },
+ { "PE9", 4, 9, { "gpio_in", "gpio_out", "csi", "ts", NULL, NULL, "eint" }, 6, 9, 2 },
+ { "PE10", 4, 10, { "gpio_in", "gpio_out", "csi", "ts", NULL, NULL, "eint" }, 6, 10, 2 },
+ { "PE11", 4, 11, { "gpio_in", "gpio_out", "csi", "ts", NULL, NULL, "eint" }, 6, 11, 2 },
+ { "PE12", 4, 12, { "gpio_in", "gpio_out", "csi", "ts", NULL, NULL, "eint" }, 6, 12, 2 },
+ { "PE13", 4, 13, { "gpio_in", "gpio_out", "csi", "ts", NULL, NULL, "eint" }, 6, 13, 2 },
+ { "PE14", 4, 14, { "gpio_in", "gpio_out", "csi", "ts", NULL, NULL, "eint" }, 6, 14, 2 },
+ { "PE15", 4, 15, { "gpio_in", "gpio_out", "csi", "ts", NULL, NULL, "eint" }, 6, 15, 2 },
+ { "PE16", 4, 16, { "gpio_in", "gpio_out", "csi", "i2c4", NULL, NULL, "eint" }, 6, 16, 2 },
+ { "PE17", 4, 17, { "gpio_in", "gpio_out", "csi", "i2c4", NULL, NULL, "eint" }, 6, 17, 2 },
+
+ { "PF0", 5, 0, { "gpio_in", "gpio_out", "mmc0" } },
+ { "PF1", 5, 1, { "gpio_in", "gpio_out", "mmc0" } },
+ { "PF2", 5, 2, { "gpio_in", "gpio_out", "mmc0", "uart0" } },
+ { "PF3", 5, 3, { "gpio_in", "gpio_out", "mmc0" } },
+ { "PF4", 5, 4, { "gpio_in", "gpio_out", "mmc0", "uart0" } },
+ { "PF5", 5, 5, { "gpio_in", "gpio_out", "mmc0" } },
+
+ { "PG0", 6, 0, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "eint" }, 6, 0, 3 },
+ { "PG1", 6, 1, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "eint" }, 6, 1, 3 },
+ { "PG2", 6, 2, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "eint" }, 6, 2, 3 },
+ { "PG3", 6, 3, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "eint" }, 6, 3, 3 },
+ { "PG4", 6, 4, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "eint" }, 6, 4, 3 },
+ { "PG5", 6, 5, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "eint" }, 6, 5, 3 },
+ { "PG6", 6, 6, { "gpio_in", "gpio_out", "uart2", NULL, NULL, NULL, "eint" }, 6, 6, 3 },
+ { "PG7", 6, 7, { "gpio_in", "gpio_out", "uart2", NULL, NULL, NULL, "eint" }, 6, 7, 3 },
+ { "PG8", 6, 8, { "gpio_in", "gpio_out", "uart2", NULL, NULL, NULL, "eint" }, 6, 8, 3 },
+ { "PG9", 6, 9, { "gpio_in", "gpio_out", "uart2", NULL, NULL, NULL, "eint" }, 6, 9, 3 },
+ { "PG10", 6, 10, { "gpio_in", "gpio_out", "i2c3", NULL, NULL, NULL, "eint" }, 6, 10, 3 },
+ { "PG11", 6, 11, { "gpio_in", "gpio_out", "i2c3", NULL, NULL, NULL, "eint" }, 6, 11, 3 },
+ { "PG12", 6, 12, { "gpio_in", "gpio_out", "uart4", NULL, NULL, NULL, "eint" }, 6, 12, 3 },
+ { "PG13", 6, 13, { "gpio_in", "gpio_out", "uart4", NULL, NULL, NULL, "eint" }, 6, 13, 3 },
+ { "PG14", 6, 14, { "gpio_in", "gpio_out", "uart4", NULL, NULL, NULL, "eint" }, 6, 14, 3 },
+ { "PG15", 6, 15, { "gpio_in", "gpio_out", "uart4", NULL, NULL, NULL, "eint" }, 6, 15, 3 },
+
+ { "PH0", 7, 0, { "gpio_in", "gpio_out", "i2c0" } },
+ { "PH1", 7, 1, { "gpio_in", "gpio_out", "i2c0" } },
+ { "PH2", 7, 2, { "gpio_in", "gpio_out", "i2c1" } },
+ { "PH3", 7, 3, { "gpio_in", "gpio_out", "i2c1" } },
+ { "PH4", 7, 4, { "gpio_in", "gpio_out", "i2c2" } },
+ { "PH5", 7, 5, { "gpio_in", "gpio_out", "i2c2" } },
+ { "PH6", 7, 6, { "gpio_in", "gpio_out", "pwm0" } },
+ { "PH8", 7, 8, { "gpio_in", "gpio_out", NULL, "pwm1", NULL, NULL, "eint" }, 6, 8, 4 },
+ { "PH9", 7, 9, { "gpio_in", "gpio_out", NULL, "pwm1", NULL, NULL, "eint" }, 6, 9, 4 },
+ { "PH10", 7, 10, { "gpio_in", "gpio_out", NULL, "pwm2", NULL, NULL, "eint" }, 6, 10, 4 },
+ { "PH11", 7, 11, { "gpio_in", "gpio_out", NULL, "pwm2", NULL, NULL, "eint" }, 6, 11, 4 },
+ { "PH12", 7, 12, { "gpio_in", "gpio_out", "uart0", "spi3", NULL, NULL, "eint" }, 6, 12, 4 },
+ { "PH13", 7, 13, { "gpio_in", "gpio_out", "uart0", "spi3", NULL, NULL, "eint" }, 6, 13, 4 },
+ { "PH14", 7, 14, { "gpio_in", "gpio_out", "spi3", NULL, NULL, NULL, "eint" }, 6, 14, 4 },
+ { "PH15", 7, 15, { "gpio_in", "gpio_out", "spi3", NULL, NULL, NULL, "eint" }, 6, 15, 4 },
+ { "PH16", 7, 16, { "gpio_in", "gpio_out", "spi3", NULL, NULL, NULL, "eint" }, 6, 16, 4 },
+ { "PH17", 7, 17, { "gpio_in", "gpio_out", "spi3", NULL, NULL, NULL, "eint" }, 6, 17, 4 },
+ { "PH18", 7, 18, { "gpio_in", "gpio_out", "spi3", NULL, NULL, NULL, "eint" }, 6, 18, 4 },
+ { "PH19", 7, 19, { "gpio_in", "gpio_out", "hdmi" } },
+ { "PH20", 7, 20, { "gpio_in", "gpio_out", "hdmi" } },
+ { "PH21", 7, 21, { "gpio_in", "gpio_out", "hdmi" } },
+};
+
+static const struct sunxi_gpio_pins a80_r_pins[] = {
+ { "PL0", 0, 0, { "gpio_in", "gpio_out", NULL, "s_uart", NULL, NULL, "eint" }, 6, 0, 0 },
+ { "PL1", 0, 1, { "gpio_in", "gpio_out", NULL, "s_uart", NULL, NULL, "eint" }, 6, 1, 0 },
+ { "PL2", 0, 2, { "gpio_in", "gpio_out", NULL, "s_jtag", NULL, NULL, "eint" }, 6, 2, 0 },
+ { "PL3", 0, 3, { "gpio_in", "gpio_out", NULL, "s_jtag", NULL, NULL, "eint" }, 6, 3, 0 },
+ { "PL4", 0, 4, { "gpio_in", "gpio_out", NULL, "s_jtag", NULL, NULL, "eint" }, 6, 4, 0 },
+ { "PL5", 0, 5, { "gpio_in", "gpio_out", NULL, "s_jtag", NULL, NULL, "eint" }, 6, 5, 0 },
+ { "PL6", 0, 6, { "gpio_in", "gpio_out", NULL, "s_cir_rx", NULL, NULL, "eint" }, 6, 6, 0 },
+ { "PL7", 0, 7, { "gpio_in", "gpio_out", NULL, "1wire", NULL, NULL, "eint" }, 6, 7, 0 },
+ { "PL8", 0, 8, { "gpio_in", "gpio_out", "s_ps2", NULL, NULL, NULL, "eint" }, 6, 8, 0 },
+ { "PL9", 0, 9, { "gpio_in", "gpio_out", "s_ps2", NULL, NULL, NULL, "eint" }, 6, 9, 0 },
+
+ { "PM0", 1, 0, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "eint" }, 6, 0, 1 },
+ { "PM1", 1, 1, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "eint" }, 6, 1, 1 },
+ { "PM2", 1, 2, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "eint" }, 6, 2, 1 },
+ { "PM3", 1, 3, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "eint" }, 6, 3, 1 },
+ { "PM4", 1, 4, { "gpio_in", "gpio_out", NULL, "s_i2s1", NULL, NULL, "eint" }, 6, 4, 1 },
+ { "PM8", 1, 8, { "gpio_in", "gpio_out", NULL, "s_i2c1", NULL, NULL, "eint" }, 6, 8, 1 },
+ { "PM9", 1, 9, { "gpio_in", "gpio_out", NULL, "s_i2c1", NULL, NULL, "eint" }, 6, 9, 1 },
+ { "PM10", 1, 10, { "gpio_in", "gpio_out", "s_i2s0", "s_i2s1" } },
+ { "PM11", 1, 11, { "gpio_in", "gpio_out", "s_i2s0", "s_i2s1" } },
+ { "PM12", 1, 12, { "gpio_in", "gpio_out", "s_i2s0", "s_i2s1" } },
+ { "PM13", 1, 13, { "gpio_in", "gpio_out", "s_i2s0", "s_i2s1" } },
+ { "PM14", 1, 14, { "gpio_in", "gpio_out", "s_i2s0", "s_i2s1" } },
+ { "PM15", 1, 15, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "eint" }, 6, 15, 1 },
+
+ { "PN0", 2, 0, { "gpio_in", "gpio_out", "s_i2c0", "s_rsb" } },
+ { "PN1", 2, 1, { "gpio_in", "gpio_out", "s_i2c0", "s_rsb" } },
+};
+
+const struct sunxi_gpio_padconf sun9i_a80_padconf = {
+ .npins = __arraycount(a80_pins),
+ .pins = a80_pins,
+};
+
+const struct sunxi_gpio_padconf sun9i_a80_r_padconf = {
+ .npins = __arraycount(a80_r_pins),
+ .pins = a80_r_pins,
+};
Index: src/sys/arch/arm/sunxi/sun9i_a80_mmcclk.c
diff -u /dev/null src/sys/arch/arm/sunxi/sun9i_a80_mmcclk.c:1.1
--- /dev/null Sun Oct 8 18:00:36 2017
+++ src/sys/arch/arm/sunxi/sun9i_a80_mmcclk.c Sun Oct 8 18:00:36 2017
@@ -0,0 +1,100 @@
+/* $NetBSD: sun9i_a80_mmcclk.c,v 1.1 2017/10/08 18:00:36 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: sun9i_a80_mmcclk.c,v 1.1 2017/10/08 18:00:36 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/sunxi/sunxi_ccu.h>
+
+#define SDC_COMM(port) (0x04 * (port))
+
+static int sun9i_a80_mmcclk_match(device_t, cfdata_t, void *);
+static void sun9i_a80_mmcclk_attach(device_t, device_t, void *);
+
+static const char * compatible[] = {
+ "allwinner,sun9i-a80-mmc-config-clk",
+ NULL
+};
+
+CFATTACH_DECL_NEW(sunxi_a80_mmcclk, sizeof(struct sunxi_ccu_softc),
+ sun9i_a80_mmcclk_match, sun9i_a80_mmcclk_attach, NULL, NULL);
+
+static struct sunxi_ccu_reset sun9i_a80_mmcclk_resets[] = {
+ SUNXI_CCU_RESET(0, SDC_COMM(0), 18),
+ SUNXI_CCU_RESET(1, SDC_COMM(1), 18),
+ SUNXI_CCU_RESET(2, SDC_COMM(2), 18),
+ SUNXI_CCU_RESET(3, SDC_COMM(3), 18),
+};
+
+static struct sunxi_ccu_clk sun9i_a80_mmcclk_clks[] = {
+ SUNXI_CCU_GATE(0, "mmc0_config", "ahb", SDC_COMM(0), 16),
+ SUNXI_CCU_GATE(1, "mmc1_config", "ahb", SDC_COMM(1), 16),
+ SUNXI_CCU_GATE(2, "mmc2_config", "ahb", SDC_COMM(2), 16),
+ SUNXI_CCU_GATE(3, "mmc3_config", "ahb", SDC_COMM(3), 16),
+};
+
+static int
+sun9i_a80_mmcclk_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+sun9i_a80_mmcclk_attach(device_t parent, device_t self, void *aux)
+{
+ struct sunxi_ccu_softc * const sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+
+ sc->sc_dev = self;
+ sc->sc_phandle = faa->faa_phandle;
+ sc->sc_bst = faa->faa_bst;
+
+ sc->sc_resets = sun9i_a80_mmcclk_resets;
+ sc->sc_nresets = __arraycount(sun9i_a80_mmcclk_resets);
+
+ sc->sc_clks = sun9i_a80_mmcclk_clks;
+ sc->sc_nclks = __arraycount(sun9i_a80_mmcclk_clks);
+
+ if (sunxi_ccu_attach(sc) != 0)
+ return;
+
+ aprint_naive("\n");
+ aprint_normal(": A80 SD/MMC-COMM\n");
+
+ sunxi_ccu_print(sc);
+}
