Module Name: src Committed By: jmcneill Date: Sat Oct 7 15:12:36 UTC 2017
Modified Files: src/sys/arch/arm/sunxi: files.sunxi sun4i_a10_ccu.c Added Files: src/sys/arch/arm/sunxi: sunxi_sata.c Log Message: Add A10/A20 SATA support To generate a diff of this commit: cvs rdiff -u -r1.29 -r1.30 src/sys/arch/arm/sunxi/files.sunxi cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/sunxi/sun4i_a10_ccu.c cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/sunxi/sunxi_sata.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/arm/sunxi/files.sunxi diff -u src/sys/arch/arm/sunxi/files.sunxi:1.29 src/sys/arch/arm/sunxi/files.sunxi:1.30 --- src/sys/arch/arm/sunxi/files.sunxi:1.29 Sat Oct 7 13:28:59 2017 +++ src/sys/arch/arm/sunxi/files.sunxi Sat Oct 7 15:12:35 2017 @@ -1,4 +1,4 @@ -# $NetBSD: files.sunxi,v 1.29 2017/10/07 13:28:59 jmcneill Exp $ +# $NetBSD: files.sunxi,v 1.30 2017/10/07 15:12:35 jmcneill Exp $ # # Configuration info for Allwinner sunxi family SoCs # @@ -195,6 +195,10 @@ device sunxithermal: sysmon_envsys, sysm attach sunxithermal at fdt with sunxi_thermal file arch/arm/sunxi/sunxi_thermal.c sunxi_thermal +# SATA +attach ahcisata at fdt with sunxi_sata +file arch/arm/sunxi/sunxi_sata.c sunxi_sata + # SOC parameters defflag opt_soc.h SOC_SUNXI defflag opt_soc.h SOC_SUN4I: SOC_SUNXI Index: src/sys/arch/arm/sunxi/sun4i_a10_ccu.c diff -u src/sys/arch/arm/sunxi/sun4i_a10_ccu.c:1.2 src/sys/arch/arm/sunxi/sun4i_a10_ccu.c:1.3 --- src/sys/arch/arm/sunxi/sun4i_a10_ccu.c:1.2 Sat Oct 7 12:22:29 2017 +++ src/sys/arch/arm/sunxi/sun4i_a10_ccu.c Sat Oct 7 15:12:35 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: sun4i_a10_ccu.c,v 1.2 2017/10/07 12:22:29 jmcneill Exp $ */ +/* $NetBSD: sun4i_a10_ccu.c,v 1.3 2017/10/07 15:12:35 jmcneill Exp $ */ /*- * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca> @@ -28,7 +28,7 @@ #include <sys/cdefs.h> -__KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.2 2017/10/07 12:22:29 jmcneill Exp $"); +__KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.3 2017/10/07 15:12:35 jmcneill Exp $"); #include <sys/param.h> #include <sys/bus.h> @@ -55,6 +55,7 @@ __KERNEL_RCSID(1, "$NetBSD: sun4i_a10_cc #define SD1_SCLK_CFG_REG 0x08c #define SD2_SCLK_CFG_REG 0x090 #define SD3_SCLK_CFG_REG 0x094 +#define SATA_CFG_REG 0x0c8 #define USBPHY_CFG_REG 0x0cc #define BE_CFG_REG 0x104 #define FE_CFG_REG 0x10c @@ -93,6 +94,7 @@ static const char *ahb_parents[] = { "ax static const char *apb0_parents[] = { "ahb" }; static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc" }; static const char *mod_parents[] = { "osc24m", "pll_periph", "pll_ddr" }; +static const char *sata_parents[] = { "pll6_periph_sata", "external" }; static const struct sunxi_ccu_nkmp_tbl sun4i_a10_ac_dig_table[] = { { 24576000, 86, 0, 21, 3 }, @@ -145,6 +147,13 @@ static struct sunxi_ccu_clk sun4i_a10_cc __BIT(14), /* enable */ 0), + SUNXI_CCU_DIV_GATE(A10_CLK_SATA, "sata", sata_parents, + SATA_CFG_REG, /* reg */ + 0, /* div */ + __BIT(24), /* sel */ + __BIT(31), /* enable */ + 0), + SUNXI_CCU_DIV(A10_CLK_CPU, "cpu", cpu_parents, CPU_AHB_APB0_CFG_REG, /* reg */ 0, /* div */ Added files: Index: src/sys/arch/arm/sunxi/sunxi_sata.c diff -u /dev/null src/sys/arch/arm/sunxi/sunxi_sata.c:1.1 --- /dev/null Sat Oct 7 15:12:36 2017 +++ src/sys/arch/arm/sunxi/sunxi_sata.c Sat Oct 7 15:12:35 2017 @@ -0,0 +1,125 @@ +/* $NetBSD: sunxi_sata.c,v 1.1 2017/10/07 15:12:35 jmcneill Exp $ */ + +/*- + * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <sys/cdefs.h> + +__KERNEL_RCSID(0, "$NetBSD: sunxi_sata.c,v 1.1 2017/10/07 15:12:35 jmcneill Exp $"); + +#include <sys/param.h> +#include <sys/bus.h> +#include <sys/device.h> +#include <sys/intr.h> +#include <sys/systm.h> + +#include <dev/ata/atavar.h> +#include <dev/ic/ahcisatavar.h> + +#include <dev/fdt/fdtvar.h> + +static const char * compatible[] = { + "allwinner,sun4i-a10-ahci", + NULL +}; + +#define SUNXI_SATA_DMACR(port) (0x170 + AHCI_P_OFFSET(port)) + +static void +sunxi_sata_channel_start(struct ahci_softc *sc, struct ata_channel *chp) +{ + const bus_size_t dma_reg = SUNXI_SATA_DMACR(chp->ch_channel); + uint32_t val; + + val = AHCI_READ(sc, dma_reg); + val &= ~0xff00; + val |= 0x4400; + AHCI_WRITE(sc, dma_reg, val); +} + +static int +sunxi_sata_match(device_t parent, cfdata_t cf, void *aux) +{ + struct fdt_attach_args * const faa = aux; + + return of_match_compatible(faa->faa_phandle, compatible); +} + +static void +sunxi_sata_attach(device_t parent, device_t self, void *aux) +{ + struct ahci_softc * const sc = device_private(self); + struct fdt_attach_args * const faa = aux; + const int phandle = faa->faa_phandle; + char intrstr[128]; + struct clk *clk; + bus_addr_t addr; + bus_size_t size; + int i; + + if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { + aprint_error(": couldn't get registers\n"); + return; + } + + sc->sc_atac.atac_dev = self; + sc->sc_dmat = faa->faa_dmat; + sc->sc_ahcit = faa->faa_bst; + sc->sc_ahcis = size; + if (bus_space_map(sc->sc_ahcit, addr, size, 0, &sc->sc_ahcih) != 0) { + aprint_error(": couldn't map registers\n"); + return; + } + sc->sc_ahci_ports = 1; + sc->sc_ahci_quirks = AHCI_QUIRK_BADPMP; + sc->sc_save_init_data = true; + sc->sc_channel_start = sunxi_sata_channel_start; + + if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { + aprint_error(": failed to decode interrupt\n"); + return; + } + + for (i = 0; (clk = fdtbus_clock_get_index(phandle, i)) != NULL; i++) + if (clk_enable(clk) != 0) { + aprint_error(": couldn't enable clock #%d\n", i); + return; + } + + aprint_naive("\n"); + aprint_normal(": SATA\n"); + + if (fdtbus_intr_establish(phandle, 0, IPL_BIO, 0, ahci_intr, sc) == NULL) { + aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); + return; + } + aprint_normal_dev(self, "interrupting on %s\n", intrstr); + + ahci_attach(sc); +} + +CFATTACH_DECL_NEW(sunxi_sata, sizeof(struct ahci_softc), + sunxi_sata_match, sunxi_sata_attach, NULL, NULL);