Module Name: src Committed By: macallan Date: Sat Dec 6 14:26:40 UTC 2014
Added Files:
src/sys/arch/evbmips/ingenic: intr.c
Log Message:
timer interrupt and IPIs
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbmips/ingenic/intr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
