CVSROOT: /cvs
Module name: src
Changes by: gkoeh...@cvs.openbsd.org 2022/10/21 18:58:56
Modified files:
sys/arch/powerpc/conf: files.powerpc
sys/arch/powerpc/include: trap.h
sys/arch/powerpc/powerpc: trap.c
Added files:
sys/arch/powerpc/powerpc: vecast.S
Log message:
AltiVec assist for subnormal floats in vectors
The old CPU in a macppc traps AltiVec instructions when they encounter
denormal or subnormal floats. Emulate most of them. They operate on
vectors of 4 single-precision floats. The emulations either use
scalar operations (so vmaddfp becomes 4 of fmadds) or a formula (like
vrsqrtefp's 1 / sqrt(b) = 1 / sqrt(b * 2**126) * 2**63).
I am forgetting to emulate some instructions (at least vrfin, vrfiz,
vrfip, vrfim). If I don't emulate it, it will still cause SIGFPE.
Mac OS never emulated these instructions, but set AltiVec's "non-Java"
NJ bit (which changes all subnormal floats to zero). FreeBSD also
sets NJ; NetBSD does SIGFPE; Linux emulates them. The POWER9 running
OpenBSD/powerpc64 does them in hardware (without trapping).
ok kettenis@ miod@
