On Tuesday 28 April 2009, Thierry Reding wrote: > This second version is pretty much a rewrite.
That happens sometimes... > Some notes about the most > important changes: > > * uses per-chip states to allow more slaves to use the controller > concurrently > * rejects invalid device configurations during setup > * rejects invalid per-message and per-transfer options > * queues messages so that they can be processed one after another > - this also provides for a way to handle power-management > * omits the spioc.h (and with it the platform data structure): > - uses the platform_device.id for the bus number > - always uses 8 chipselects because that's the maximum that the core > supports All that sounds good. > I couldn't really find a way to implement per-transfer overrides for the > word size because the controller simply has no concept of word sizes. Is it > in such cases still necessary to hardwire the word size to 8 bits? Is this the http://www.opencores.org/?do=project&who=spi core? Its summary says "Variable length of transfer word up to 32 bits"; does that mean "configurable when core is synthesized" instead of truly "variable"? ------------------------------------------------------------------------------ Register Now & Save for Velocity, the Web Performance & Operations Conference from O'Reilly Media. Velocity features a full day of expert-led, hands-on workshops and two days of sessions from industry leaders in dedicated Performance & Operations tracks. Use code vel09scf and Save an extra 15% before 5/3. http://p.sf.net/sfu/velocityconf _______________________________________________ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
