On 2012-12-28 17:16, Andreas Larsson wrote: > This makes the cpu mode of the driver available outside of an FSL SOC > and even powerpc environment. This is accomplished by putting things > regarding fsl specific code and to cpm specific code within ifdefs. > > Furthermore, this adds support for the mostly register-compatible > SPICTRL core from the GRLIB VHDL IP core library normally running on > sparc. A different entry in of_fsl_spi_match matches this core and > indicates a different hardware type that is used to set up different > function pointers and special cases. The fetching of irq is changed to > work under sparc as well. > > The GRLIB core operates in cpu mode and from the driver's point of view > the important differences are that the number of bits per word might be > limited and that there might be native chipselects selected via the > added slvsel register. These differences if present are indicated by an > added capabilities register. > > Signed-off-by: Andreas Larsson <andr...@gaisler.com>
Any comments anyone? This patch takes "Approach A" discussed and supported in http://sourceforge.net/mailarchive/message.php?msg_id=30131080 Cheers, Andreas Larsson ------------------------------------------------------------------------------ Everyone hates slow websites. So do we. Make your web apps faster with AppDynamics Download AppDynamics Lite for free today: http://p.sf.net/sfu/appdyn_d2d_jan _______________________________________________ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
