Hello Trent, > There are two bits which control the CS line in the CTRL0 register: > LOCK_CS and IGNORE_CRC. The latter would be better named DEASSERT_CS > in SPI mode. > > LOCK_CS keeps CS asserted though the entire transfer. This should > always be set. The DMA code will always set it, explicitly on the > first segment of the first transfer, and then implicitly on all the > rest by never clearing the bit from the value read from the ctrl0 > register. > > The only reason to not set LOCK_CS would be to attempt an altered > protocol where CS pulses between each word. Though don't get your > hopes up if you want to do this, as the hardware doesn't appear to do > this in any sane manner. > > The code can be simplified by just setting LOCK_CS once and then not > needing to deal with it in the PIO and DMA transfer functions. > > Signed-off-by: Trent Piepho <tpie...@gmail.com> > Cc: Marek Vasut <ma...@denx.de> > Cc: Fabio Estevam <fabio.este...@freescale.com> > Cc: Shawn Guo <shawn....@linaro.org>
Will we see a V3 of this stuff? I don't want to see this lost. Best regards, Marek Vasut ------------------------------------------------------------------------------ Precog is a next-generation analytics platform capable of advanced analytics on semi-structured data. The platform includes APIs for building apps and a phenomenal toolset for data science. Developers can use our toolset for easy data analysis & visualization. Get a free account! http://www2.precog.com/precogplatform/slashdotnewsletter _______________________________________________ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
