Hi, Fabio Estevam writes: > On Tue, Apr 2, 2013 at 8:18 PM, Marek Vasut <ma...@denx.de> wrote: > > Dear Trent Piepho, > > > >> There are two bits which control the CS line in the CTRL0 register: > >> LOCK_CS and IGNORE_CRC. The latter would be better named DEASSERT_CS > >> in SPI mode. > >> > >> LOCK_CS keeps CS asserted though the entire transfer. This should > >> always be set. The DMA code will always set it, explicitly on the > >> first segment of the first transfer, and then implicitly on all the > >> rest by never clearing the bit from the value read from the ctrl0 > >> register. > >> > >> The only reason to not set LOCK_CS would be to attempt an altered > >> protocol where CS pulses between each word. Though don't get your > >> hopes up if you want to do this, as the hardware doesn't appear to do > >> this in any sane manner. > > > > Can you please elaborate on this part above? The description is very vague. > > From my experience the HW deasserts CS whenever the output fifo runs empty.
Lothar Waßmann -- ___________________________________________________________ Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10 Geschäftsführer: Matthias Kaussen Handelsregistereintrag: Amtsgericht Aachen, HRB 4996 www.karo-electronics.de | i...@karo-electronics.de ___________________________________________________________ ------------------------------------------------------------------------------ See everything from the browser to the database with AppDynamics Get end-to-end visibility with application monitoring from AppDynamics Isolate bottlenecks and diagnose root cause in seconds. Start your free trial of AppDynamics Pro today! http://pubads.g.doubleclick.net/gampad/clk?id=48808831&iu=/4140/ostg.clktrk _______________________________________________ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
