Hi，
We are now developing the 1920*1080 HD camera with CCD KAI02150 and I
am a rookie in camera design.We choose Altera EP3C25 FPGA to do video
pre-processing and
TI DM368 for further process and compression. And I am now in charge of
designing the FPGA board which is to be linked to the DSP Kit. I saw a 64MB of
DDR SDRAM memory
chip in your design to provide temporary buffering. But I wonder if it is
reasonable to use 2 pcs of 2MB asynchronous SRAM chip to replace or just add 2
pcs SRAM. Which plan shall we take?
And I am also interested in how data flows in the FPGA funtional
structure in your design and how 2A functions work in your camera. Please give
me some advice and information
in the FPGA hardware design of the HD camera.
Thank you.
Best regards,
Shawyoo Lee
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