> On Thu, May 20, 2010 at 07:54:46AM +0200, Christoph Egger wrote: > > The combined effect of MTRR and PAT memory types: > > > > PAT memory type MTRR memory type effective memory type > > UC UC, WC, WP, WT, WB UC > > UC- UC UC > > UC- WC WC > > UC- WP, WT, WB UC > > WC — WC > > WP UC UC > > WP WC UC > > WP WP WP > > WP WT UC > > WP WB WP > > WT UC UC > > WT WC, WP UC > > WT WT, WB WT > > WB UC UC > > WB WC WC > > WB WP WP > > WB WT WT > > WB WB WB > > ISTM that the effective memory type (EMT), not the PAT memory > type, should be controlled by pmap(9). MTRR and PAT should > be consistent, and no single physical page should be mapped > once with one EMT and a second time with an inconsistent EMT.
That's not how it works on x86. On x86 you specify the PAT memory type per page-level. You specify the MTRR memory type via MTRR. Where MTRR and PAT overlap, the processor combines both to the EMT using above table before it accesses the memory. > > On 20.05.10 01:15, David Young wrote: > > > Are some memory types more suitable for a DMA buffer than > > > others? > > > > For MMIO you can use either Uncachable, Uncacheable Minus > > or Write-Combine. > > Ok. What about DMA buffers? If the DMA buffer is coherent it may also be cacheable. Christoph
