>>> [cache line sizes, maybe not always 64?] >> You are correct; to cite the one example I currently have swapped >> into my brain, the Super-H used in the Dreamcast has 32-byte cache >> lines (true of the I-cache and D-cache both). > I'm curious why non-kernel components would care.
Choosing array layouts for efficient access? Choosing a stride for prefetch operations? > The question also gets amusing when the cache line size varies among > the caches. That's not all that common, but it certainly happens. Indeed! I wonder if there are caches with different cache line sizes for the same type of fetch (instructions vs data). One for opcode fetches and one for inline constants maybe? (On the Super-H, this could actually make sense; "inline" constants are not truly inline - they may be displaced significantly from the instructions accessing them.) /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mo...@rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B