Hi! I´m trying to understand interrupt priority levels using the example of x86. From what I´ve seen so far I´d say that all spl*() functions end up in either splraise() or spllower() from sys/arch/i386/i386/spl.S. What these functions actually do is not clear to me. For example, splraise() starts with this:
ENTRY(splraise) movl 4(%esp),%edx movl CPUVAR(ILEVEL),%eax cmpl %edx,%eax ja 1f movl %edx,CPUVAR(ILEVEL) ... I´m unable to find out what CPUVAR(ILEVEL) means. I would guess that something needs to happen to the APIC´s task priority register. However I can´t see any coherence just now. Thanks for help!