Le 25/11/2016 à 15:38, Maxime Villard a écrit : > I've committed the patch, but without the push/pop before iret. As I said in > the comment, the ddb ipi triggers a hardware context switch, so in fact we > don't care about overwriting %ebx before iret. > > As a general rule, and for the record: normally we should never have to worry > about the state of the registers upon exit when modifying an isr. If we had > to, > it would mean that there is already a problem. > > Now that it is committed, if someone here sees a regression, a panic or > whatever, please report it to me. > > (and thanks for the review) >
My change apparently causes CPUs that have no LAPIC to crash [1] [2]. The reason is that our x86 implementation relies a lot on it and always uses the va of the LAPIC, even when it is not there. The cpus that don't have a lapic are quite old, apparently before i486. I'm not sure whether so far we have been using the va on those precisely because we didn't care about writing to it for no reason, or if it has always been an age-old bug that I just happen to have unearthed. When it comes to [2], I'm not even sure if the cpu has at least a 82489DX, and if it implies that somehow the kernel does not properly detect it. Clearly, given how rare these CPUs are, I am not going to develop a special support for them - I wouldn't be able to test it anyway. My initial intention was to always kenter the va to a fake pa on i386 [3], just to reproduce the old behavior and rehide the bug. But now I'm wondering whether someone has a better idea, or if we simply don't care about that kind of cpu anymore. [1] http://mail-index.netbsd.org/current-users/2016/11/30/msg030542.html [2] http://mail-index.netbsd.org/port-i386/2016/12/07/msg003561.html [3] http://m00nbsd.net/garbage/lapic/nolapic.diff
