On Sun, Oct 31, 2010 at 05:10:46PM -0700, Philip Guenther wrote: > Okay, enough cleanup; time to simplify the TSS handling by moving from > TSS-per-process to TSS-per-CPU. This eliminates the need to ever change > GDT entries after startup and the associated ~4k process limit. > > Where do we place that TSS? Before, it was part of the PCB; here I've put > the primary CPU's TSS between the IDT and the primary CPU's GDT. For > secondary CPU's I place it right after the CPU's GDT. The exact location > isn't important, they just need to be in unpageable, unmanaged memory like > the GDT, so putting it next to the GDT is convenient. > > With the TSS being per-CPU, we no longer need to change the 'task busy' > flag or load the task register when doing a context switch. Instead, we > just poke into the TSS the pointer to the process's kernel stack. > > The TSS also contains the pointer to the stack used for double faults. > Previously, this was placed one page above each process's PCB. Rather > than change that on each context switch, I've just left it set to one page > above each CPU's idle process's PCB. I think we can reduce the size of > normal processes' USPACE by a page, or maybe even two, what with the PCB > shrinking, but that can wait. > > To increase speed and paranoia slightly, I've inlined pmap_activate() and > pmap_deactivate() into the asm cpu_switchto routine. That let me add a > 'free' check for the new pmap already being marked as active on the CPU; > that check earlier caught some sloppy handling of that bitmap. > > Garbage collect the hasn't-been-used-in-years GDT update IPI. > > > As before, I would like to hear tests for both real AMD and Intel CPUs; > thank you to everyone that sent results before!
Completed build ok with my 'real' amd64 box. .... Ken
