On Tue, Nov 09, 2010 at 18:19 -0800, Philip Guenther wrote:
> On Tue, Nov 9, 2010 at 10:41 AM, Mike Belopuhov <[email protected]> wrote:
> > On Sun, Oct 31, 2010 at 17:10 -0700, Philip Guenther wrote:
> ...
> >> The TSS also contains the pointer to the stack used for double faults.
> >> Previously, this was placed one page above each process's PCB. Rather
> >> than change that on each context switch, I've just left it set to one page
> >> above each CPU's idle process's PCB.
> >
> > i failed to find the code that does this. could you please point me to it.
> >
> > is it supposed to be referenced by the tss_ist[1]?
>
> No, the double-fault stack is tss_ist[0]. That's set in
> x86_64_proc0_tss_ldt_init() and x86_64_init_pcb_tss_ldt (primary vs
> secondary processor) to point into the processor's idle process
> uspace. It's the same place it points now, it's just that the patch
> changes it to only get set once, when each processor's idle process is
> created, instead of having it be a per-process value by virtue of the
> tss being per-process.
>
oh, "gd_ist == 0" is a special case:
"To enable the IST mechanism for a specific interrupt, system software
stores a non-zero value in the interrupt gate-descriptor IST-index field.
If the IST index is zero, the modified legacy stack-switching
mechanism (described in the previous section) is used."
that clears it up.
>
> > you might also want to remove disabled amd64_{get,set}_ioperm code.
>
> Good point, though I'm inclined to do that as a separate commit.
>
sure.
> >> /* exceptions */
> >> for (x = 0; x < 32; x++) {
> >> ist = (x == 8) ? 1 : 0;
> >> + // ist = (x == 8) ? 1 : (x == 2) ? 2 : 0;
> >
> > why do you need this comment? or is it a reminder to have
> > a separate stack for the NMI in the future?
>
> Yep. I was thinking of doing it as part of this diff, realized I
> didn't know how to test it, and so left it as a comment.
>
maybe you can put a bit more elaborate comment if you plan on keeping it?
anyways i'm ok with the diff.
