Hi,
the following diff adds Octeon specific opcodes support to our binutils.
For now I just added the sync opcodes which are needed for the bus
barrier routines. (From what I read this will be useful not only for SMP
but also for DMA.)
I've tested it on my Octeon machines with the syncw instruction and
everything seems fine.
Is this acceptable?
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/gnu/usr.bin/binutils-2.17/bfd/archures.c,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 archures.c
--- bfd/archures.c 24 Apr 2011 20:14:41 -0000 1.1.1.1
+++ bfd/archures.c 7 Aug 2015 15:44:40 -0000
@@ -160,6 +160,7 @@ DESCRIPTION
.#define bfd_mach_mips16 16
.#define bfd_mach_mips5 5
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
+.#define bfd_mach_mips_octeon 6501
.#define bfd_mach_mipsisa32 32
.#define bfd_mach_mipsisa32r2 33
.#define bfd_mach_mipsisa64 64
Index: bfd/bfd-in2.h
===================================================================
RCS file: /cvs/src/gnu/usr.bin/binutils-2.17/bfd/bfd-in2.h,v
retrieving revision 1.4
diff -u -p -r1.4 bfd-in2.h
--- bfd/bfd-in2.h 25 May 2015 14:56:26 -0000 1.4
+++ bfd/bfd-in2.h 7 Aug 2015 15:44:41 -0000
@@ -1758,6 +1758,7 @@ enum bfd_architecture
#define bfd_mach_mips16 16
#define bfd_mach_mips5 5
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
+#define bfd_mach_mips_octeon 6501
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33
#define bfd_mach_mipsisa64 64
Index: bfd/cpu-mips.c
===================================================================
RCS file: /cvs/src/gnu/usr.bin/binutils-2.17/bfd/cpu-mips.c,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 cpu-mips.c
--- bfd/cpu-mips.c 24 Apr 2011 20:14:41 -0000 1.1.1.1
+++ bfd/cpu-mips.c 7 Aug 2015 15:44:41 -0000
@@ -86,6 +86,7 @@ enum
I_mipsisa64,
I_mipsisa64r2,
I_sb1,
+ I_mipsocteon,
};
#define NN(index) (&arch_info_struct[(index) + 1])
@@ -118,7 +119,8 @@ static const bfd_arch_info_type arch_inf
N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
- N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0),
+ N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
+ N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, 0),
};
/* The default architecture is mips:3000, but with a machine number of
Index: bfd/elfxx-mips.c
===================================================================
RCS file: /cvs/src/gnu/usr.bin/binutils-2.17/bfd/elfxx-mips.c,v
retrieving revision 1.4
diff -u -p -r1.4 elfxx-mips.c
--- bfd/elfxx-mips.c 22 Dec 2014 14:17:22 -0000 1.4
+++ bfd/elfxx-mips.c 7 Aug 2015 15:44:42 -0000
@@ -4967,6 +4967,9 @@ _bfd_elf_mips_mach (flagword flags)
case E_MIPS_MACH_SB1:
return bfd_mach_mips_sb1;
+ case E_MIPS_MACH_OCTEON:
+ return bfd_mach_mips_octeon;
+
default:
switch (flags & EF_MIPS_ARCH)
{
@@ -9033,6 +9036,10 @@ mips_set_isa_flags (bfd *abfd)
val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
break;
+ case bfd_mach_mips_octeon:
+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
+ break;
+
case bfd_mach_mipsisa32:
val = E_MIPS_ARCH_32;
break;
@@ -10714,6 +10721,9 @@ struct mips_mach_extension {
are ordered topologically with MIPS I extensions listed last. */
static const struct mips_mach_extension mips_mach_extensions[] = {
+ /* MIPS64r2 extensions. */
+ { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
+
/* MIPS64 extensions. */
{ bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
{ bfd_mach_mips_sb1, bfd_mach_mipsisa64 },
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/gnu/usr.bin/binutils-2.17/gas/config/tc-mips.c,v
retrieving revision 1.3
diff -u -p -r1.3 tc-mips.c
--- gas/config/tc-mips.c 7 Jan 2013 22:23:05 -0000 1.3
+++ gas/config/tc-mips.c 7 Aug 2015 15:44:43 -0000
@@ -14402,6 +14402,9 @@ static const struct mips_cpu_info mips_c
{ "loongson2f", 0, ISA_L2F, CPU_L2F },
*/
+ /* Cavium Networks Octeon CPU core */
+ { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
+
/* MIPS IV */
{ "r8000", 0, ISA_MIPS4, CPU_R8000 },
{ "r10000", 0, ISA_MIPS4, CPU_R10000 },
Index: include/elf/mips.h
===================================================================
RCS file: /cvs/src/gnu/usr.bin/binutils-2.17/include/elf/mips.h,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 mips.h
--- include/elf/mips.h 24 Apr 2011 20:14:48 -0000 1.1.1.1
+++ include/elf/mips.h 7 Aug 2015 15:44:43 -0000
@@ -212,6 +212,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
#define E_MIPS_MACH_4120 0x00870000
#define E_MIPS_MACH_4111 0x00880000
#define E_MIPS_MACH_SB1 0x008a0000
+#define E_MIPS_MACH_OCTEON 0x008b0000
#define E_MIPS_MACH_5400 0x00910000
#define E_MIPS_MACH_5500 0x00980000
#define E_MIPS_MACH_9000 0x00990000
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/gnu/usr.bin/binutils-2.17/include/opcode/mips.h,v
retrieving revision 1.2
diff -u -p -r1.2 mips.h
--- include/opcode/mips.h 24 Apr 2011 20:19:25 -0000 1.2
+++ include/opcode/mips.h 7 Aug 2015 15:44:43 -0000
@@ -466,6 +466,12 @@ struct mips_opcode
#define INSN_ISA32R2 0x00000080
#define INSN_ISA64R2 0x00000100
+/* Masks used for Chip specific instructions. */
+#define INSN_CHIP_MASK 0xc3ff0f20
+
+/* Cavium Networks Octeon instructions. */
+#define INSN_OCTEON 0x00000800
+
/* Masks used for MIPS-defined ASEs. */
#define INSN_ASE_MASK 0x0400f000
@@ -478,8 +484,6 @@ struct mips_opcode
/* MDMX ASE */
#define INSN_MDMX 0x00008000
-/* Chip specific instructions. These are bitmasks. */
-
/* MIPS R4650 instruction. */
#define INSN_4650 0x00010000
/* LSI R4010 instruction. */
@@ -549,6 +553,7 @@ struct mips_opcode
#define CPU_MIPS64 64
#define CPU_MIPS64R2 65
#define CPU_SB1 12310201 /* octal 'SB', 01. */
+#define CPU_OCTEON 6501
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
@@ -570,6 +575,7 @@ struct mips_opcode
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
+ || (cpu == CPU_OCTEON && ((insn)->membership & INSN_OCTEON) != 0) \
|| 0) /* Please keep this term for easier source merging. */
/* This is a list of macro expanded instructions.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/gnu/usr.bin/binutils-2.17/opcodes/mips-opc.c,v
retrieving revision 1.3
diff -u -p -r1.3 mips-opc.c
--- opcodes/mips-opc.c 22 Aug 2012 13:27:23 -0000 1.3
+++ opcodes/mips-opc.c 7 Aug 2015 15:44:43 -0000
@@ -109,6 +109,7 @@ Software Foundation, 51 Franklin Street
#define N5 (INSN_5400 | INSN_5500)
#define N54 INSN_5400
#define N55 INSN_5500
+#define IOCT INSN_OCTEON
#define G1 (T3 \
)
@@ -1182,6 +1183,10 @@ const struct mips_opcode mips_builtin_op
{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b,
0, I2 }, /* same */
{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0,
I2 }, /* as swr */
{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S,
0, I4|I33 },
+{"synciobdma", "", 0x0000008f, 0xffffffff, INSN_SYNC, 0,
IOCT },
+{"syncs", "", 0x0000018f, 0xffffffff, INSN_SYNC, 0,
IOCT },
+{"syncw", "", 0x0000010f, 0xffffffff, INSN_SYNC, 0,
IOCT },
+{"syncws", "", 0x0000014f, 0xffffffff, INSN_SYNC, 0,
IOCT },
{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC,
0, I2|G1 },
{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC,
0, I2 },
{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC,
0, I2 },
