So the ARMv7 ARM says in B4.2.2:
- on an implementation with separate data and instruction TLBs, any
unified TLB operation operates on both TLBs
- on an implementation with a unified TLB, any instruction TLB
operation, and any data TLB operation, operates on the unified TLB
- ARM deprecates use of instruction TLB operations and data TLB
operations, and recommends that software always uses the unified
TLB operations.
It seems that All the Cortex-A CPUs, with the exception of the
Cortex-A8 have a unified TLB. Since the non-unified TLB operations
are deprecated, and using the unified TLB operations leads to some
code simplifications, I think it makes sense to switch armv7 to these.
This might be a slight pessimisation on Cortex-A8, although I'm not
sure it will be noticable.
Thoughts?
Tested on Cortex-A9. Would be nice if somebody could test this on
Cortex-A8.
Index: arch/arm/arm/cpufunc_asm_armv7.S
===================================================================
RCS file: /cvs/src/sys/arch/arm/arm/cpufunc_asm_armv7.S,v
retrieving revision 1.10
diff -u -p -r1.10 cpufunc_asm_armv7.S
--- arch/arm/arm/cpufunc_asm_armv7.S 25 Apr 2016 04:46:56 -0000 1.10
+++ arch/arm/arm/cpufunc_asm_armv7.S 1 Aug 2016 14:34:36 -0000
@@ -55,15 +55,14 @@ ENTRY(armv7_setttb)
* TLB functions
*/
ENTRY(armv7_tlb_flushID_SE)
- mcr CP15_DTLBIMVA /* flush D tlb single entry */
- mcr CP15_ITLBIMVA /* flush I tlb single entry */
+ mcr CP15_TLBIMVA(r0) /* flush unified tlb single entry */
mcr CP15_BPIMVA /* flush va from BP */
dsb sy
isb sy
mov pc, lr
ENTRY(armv7_tlb_flushI_SE)
- mcr CP15_ITLBIMVA /* flush I tlb single entry */
+ mcr CP15_TLBIMVA(r0) /* flush unified tlb single entry */
mcr CP15_BPIMVA /* flush va from BP */
dsb sy
isb sy
@@ -73,27 +72,27 @@ ENTRY(armv7_tlb_flushI_SE)
* TLB functions
*/
ENTRY(armv7_tlb_flushID)
- mcr CP15_TLBIALL(r0) /* flush I+D tlb */
+ mcr CP15_TLBIALL(r0) /* flush unified tlb */
mcr CP15_BPIALL /* Flush BP cache */
dsb sy
isb sy
mov pc, lr
ENTRY(armv7_tlb_flushI)
- mcr CP15_ITLBIALL /* flush I tlb */
+ mcr CP15_TLBIALL(r0) /* flush unified tlb */
mcr CP15_BPIALL /* Flush BP cache */
dsb sy
isb sy
mov pc, lr
ENTRY(armv7_tlb_flushD)
- mcr CP15_DTLBIALL /* flush D tlb */
+ mcr CP15_TLBIALL(r0) /* flush unified tlb */
dsb sy
isb sy
mov pc, lr
ENTRY(armv7_tlb_flushD_SE)
- mcr CP15_DTLBIMVA /* flush D tlb single entry */
+ mcr CP15_TLBIMVA(r0) /* flush unified tlb single entry */
dsb sy
isb sy
mov pc, lr
Index: arch/arm/arm/pmap7.c
===================================================================
RCS file: /cvs/src/sys/arch/arm/arm/pmap7.c,v
retrieving revision 1.31
diff -u -p -r1.31 pmap7.c
--- arch/arm/arm/pmap7.c 31 Jul 2016 22:27:07 -0000 1.31
+++ arch/arm/arm/pmap7.c 1 Aug 2016 14:34:37 -0000
@@ -1028,12 +1028,8 @@ pmap_clearbit(struct vm_page *pg, u_int
*ptep = npte;
PTE_SYNC(ptep);
/* Flush the TLB entry if a current pmap. */
- if (l2pte_valid(opte)) {
- if (PV_BEEN_EXECD(oflags))
- pmap_tlb_flushID_SE(pm, pv->pv_va);
- else
- pmap_tlb_flushD_SE(pm, pv->pv_va);
- }
+ if (l2pte_valid(opte))
+ pmap_tlb_flushID_SE(pm, pv->pv_va);
}
NPDEBUG(PDB_BITS,
@@ -1281,7 +1277,6 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_
ptep = &l2b->l2b_kva[l2pte_index(va)];
opte = *ptep;
npte = pa;
- oflags = 0;
if (opte != 0) { /* not l2pte_valid!!! MIOD */
/*
@@ -1367,7 +1362,6 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_
* must remove it from the PV list
*/
pve = pmap_remove_pv(opg, pm, va);
- oflags = pve->pv_flags;
} else
if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){
if ((flags & PMAP_CANFAIL) == 0)
@@ -1397,8 +1391,6 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_
* at this address.
*/
pve = pmap_remove_pv(opg, pm, va);
- oflags = pve->pv_flags;
-
pool_put(&pmap_pv_pool, pve);
}
}
@@ -1449,12 +1441,8 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_
}
}
- if (l2pte_valid(opte)) {
- if (PV_BEEN_EXECD(oflags))
- pmap_tlb_flushID_SE(pm, va);
- else
- pmap_tlb_flushD_SE(pm, va);
- }
+ if (l2pte_valid(opte))
+ pmap_tlb_flushID_SE(pm, va);
}
/*
@@ -1480,7 +1468,7 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd
struct l2_bucket *l2b;
vaddr_t next_bucket;
pt_entry_t *ptep;
- u_int mappings, is_exec;
+ u_int mappings;
NPDEBUG(PDB_REMOVE, printf("pmap_remove: pmap=%p sva=%08lx eva=%08lx\n",
pm, sva, eva));
@@ -1520,7 +1508,6 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd
pm->pm_stats.resident_count--;
pa = l2pte_pa(pte);
- is_exec = 0;
/*
* Update flags. In a number of circumstances,
@@ -1531,10 +1518,8 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd
if (pg != NULL) {
struct pv_entry *pve;
pve = pmap_remove_pv(pg, pm, sva);
- if (pve != NULL) {
- is_exec = PV_BEEN_EXECD(pve->pv_flags);
+ if (pve != NULL)
pool_put(&pmap_pv_pool, pve);
- }
}
/*
@@ -1547,12 +1532,8 @@ pmap_remove(pmap_t pm, vaddr_t sva, vadd
*ptep = L2_TYPE_INV;
PTE_SYNC(ptep);
- if (l2pte_valid(pte)) {
- if (is_exec)
- pmap_tlb_flushID_SE(pm, sva);
- else
- pmap_tlb_flushD_SE(pm, sva);
- }
+ if (l2pte_valid(pte))
+ pmap_tlb_flushID_SE(pm, sva);
sva += PAGE_SIZE;
ptep++;
@@ -1801,12 +1782,8 @@ NPDEBUG(PDB_PROTECT, printf("\n"));
if (flush >= 0) {
flush++;
- if (l2pte_valid(opte)) {
- if (PV_BEEN_EXECD(f))
- cpu_tlb_flushID_SE(sva);
- else
- cpu_tlb_flushD_SE(sva);
- }
+ if (l2pte_valid(opte))
+ cpu_tlb_flushID_SE(sva);
} else
flags |= f;
}
@@ -1816,12 +1793,9 @@ NPDEBUG(PDB_PROTECT, printf("\n"));
}
}
- if (flush < 0) {
- if (PV_BEEN_EXECD(flags))
- pmap_tlb_flushID(pm);
- else
- pmap_tlb_flushD(pm);
- }
+ if (flush < 0)
+ pmap_tlb_flushID(pm);
+
NPDEBUG(PDB_PROTECT, printf("\n"));
}
