On Tue, Aug 02, 2016 at 01:43:10PM +0200, Mark Kettenis wrote:
> > Date: Tue, 2 Aug 2016 02:02:57 +1000
> > From: Jonathan Gray <[email protected]>
>
> Adding back tech@ just in case a knwoledgable person there wants to
> chime in...
>
> > On Mon, Aug 01, 2016 at 05:10:48PM +0200, Mark Kettenis wrote:
> > > So the ARMv7 ARM says in B4.2.2:
> > >
> > > - on an implementation with separate data and instruction TLBs, any
> > > unified TLB operation operates on both TLBs
> > >
> > > - on an implementation with a unified TLB, any instruction TLB
> > > operation, and any data TLB operation, operates on the unified TLB
> > >
> > > - ARM deprecates use of instruction TLB operations and data TLB
> > > operations, and recommends that software always uses the unified
> > > TLB operations.
> > >
> > > It seems that All the Cortex-A CPUs, with the exception of the
> > > Cortex-A8 have a unified TLB. Since the non-unified TLB operations
> > > are deprecated, and using the unified TLB operations leads to some
> > > code simplifications, I think it makes sense to switch armv7 to these.
> > > This might be a slight pessimisation on Cortex-A8, although I'm not
> > > sure it will be noticable.
> > >
> > > Thoughts?
> > >
> > > Tested on Cortex-A9. Would be nice if somebody could test this on
> > > Cortex-A8.
> >
> > We could just drop the I and D specific functions like FreeBSD did?
> >
> > /*
> > * TLB functions. ARMv7 does all TLB ops based on a unified TLB
> > model
> > * whether the hardware implements separate I+D or not, so we use
> > the
> > * same 'ID' functions for all 3 variations.
> > */
> >
> > armv7_tlb_flushID, /* tlb_flushID */
> > armv7_tlb_flushID_SE, /* tlb_flushID_SE */
> > armv7_tlb_flushID, /* tlb_flushD */
> > armv7_tlb_flushID_SE, /* tlb_flushD_SE */
> >
> > https://lists.freebsd.org/pipermail/freebsd-arm/2014-March/007849.html
>
> I think it makes sense to keep the distinction betwwen the ID and D
> variants for now. The ID variants also flush the branch predictor
> wheras the D variants don't.
>
> That raises some question about my simplifications of the armv7 pmap.
> Those replace the conditional executation of ID or D variants with
> unconditional executaion of D variants. I think that that is still
> worth doing. In theory there is some additional overhead for flushing
> the branch prediction. But the elemination of the branch instructions
> will at least partly compensate for that. And on most, if not all,
> Cortex CPUs flushing the branch predictor isn't necessary. So on
> those we can simply change the function pointers to always use the D
> variants. I'll do that in a fllowup diff.
>
> So, as a first step I'd like to commit the diff below.
>
> ok?
You seem to be missing a cpufunc.c diff, I think this is
what you meant to send?
In which case ok jsg@
Index: cpufunc.c
===================================================================
RCS file: /cvs/src/sys/arch/arm/arm/cpufunc.c,v
retrieving revision 1.42
diff -u -p -r1.42 cpufunc.c
--- cpufunc.c 31 Jul 2016 03:49:51 -0000 1.42
+++ cpufunc.c 2 Aug 2016 12:09:04 -0000
@@ -109,8 +109,8 @@ struct cpu_functions armv7_cpufuncs = {
armv7_tlb_flushID, /* tlb_flushID */
armv7_tlb_flushID_SE, /* tlb_flushID_SE */
- armv7_tlb_flushI, /* tlb_flushI */
- armv7_tlb_flushI_SE, /* tlb_flushI_SE */
+ armv7_tlb_flushID, /* tlb_flushI */
+ armv7_tlb_flushID_SE, /* tlb_flushI_SE */
armv7_tlb_flushD, /* tlb_flushD */
armv7_tlb_flushD_SE, /* tlb_flushD_SE */
Index: cpufunc_asm_armv7.S
===================================================================
RCS file: /cvs/src/sys/arch/arm/arm/cpufunc_asm_armv7.S,v
retrieving revision 1.10
diff -u -p -r1.10 cpufunc_asm_armv7.S
--- cpufunc_asm_armv7.S 25 Apr 2016 04:46:56 -0000 1.10
+++ cpufunc_asm_armv7.S 2 Aug 2016 12:09:04 -0000
@@ -45,7 +45,7 @@ ENTRY(armv7_setttb)
isb sy
mcr CP15_TTBR0(r0) /* load new TTB */
- mcr CP15_TLBIALL(r0) /* invalidate I+D TLBs */
+ mcr CP15_TLBIALL(r0) /* invalidate unified TLB */
dsb sy
isb sy
@@ -55,45 +55,27 @@ ENTRY(armv7_setttb)
* TLB functions
*/
ENTRY(armv7_tlb_flushID_SE)
- mcr CP15_DTLBIMVA /* flush D tlb single entry */
- mcr CP15_ITLBIMVA /* flush I tlb single entry */
+ mcr CP15_TLBIMVA(r0) /* flush unified tlb single entry */
mcr CP15_BPIMVA /* flush va from BP */
dsb sy
isb sy
mov pc, lr
-ENTRY(armv7_tlb_flushI_SE)
- mcr CP15_ITLBIMVA /* flush I tlb single entry */
- mcr CP15_BPIMVA /* flush va from BP */
- dsb sy
- isb sy
- mov pc, lr
-
-/*
- * TLB functions
- */
ENTRY(armv7_tlb_flushID)
- mcr CP15_TLBIALL(r0) /* flush I+D tlb */
+ mcr CP15_TLBIALL(r0) /* flush unified tlb */
mcr CP15_BPIALL /* Flush BP cache */
dsb sy
isb sy
mov pc, lr
-ENTRY(armv7_tlb_flushI)
- mcr CP15_ITLBIALL /* flush I tlb */
- mcr CP15_BPIALL /* Flush BP cache */
+ENTRY(armv7_tlb_flushD_SE)
+ mcr CP15_TLBIMVA(r0) /* flush unified tlb single entry */
dsb sy
isb sy
mov pc, lr
ENTRY(armv7_tlb_flushD)
- mcr CP15_DTLBIALL /* flush D tlb */
- dsb sy
- isb sy
- mov pc, lr
-
-ENTRY(armv7_tlb_flushD_SE)
- mcr CP15_DTLBIMVA /* flush D tlb single entry */
+ mcr CP15_TLBIALL(r0) /* flush unified tlb */
dsb sy
isb sy
mov pc, lr
@@ -251,7 +233,7 @@ ENTRY(armv7_context_switch)
isb sy
mcr CP15_TTBR0(r0) /* set the new TTB */
- mcr CP15_TLBIALL(r0) /* and flush the I+D tlbs */
+ mcr CP15_TLBIALL(r0) /* and flush the unified tlb */
dsb sy
isb sy
mov pc, lr
