); SAEximRunCond expanded to false Errors-To: [EMAIL PROTECTED] RETRY Dear timing colleges,
At CERN we are considering the possibility of using Ethernet as a real time field bus. We may use IEEE 1588 to distribute precise UTC and Ethernet Powerlink or a similar home made product to guarantee real time. In order to have full control over the network we are thinking of designing our own hardware using FPGAs (including the physical interface). It looks like we will end by implementing 100Base-TX or 10Base-T rather than gigabit Ethernet, just because it looks much more robust and simpler to design. I am just a beginner in the Ethernet world. I have the following questions concerning the timing: 1) Two ways calibration performed in IEEE 1588 needs a symmetric path between nodes. In a presentation made by 'Timing Solutions', they say there is a 10% of asymmetry on the path for 100Base-TX. I guess this comes from the fact of using one pair for the go and a different pair for the return path. Do you have some figures for the two ways asymmetry on a single pair? http://ieee1588.nist.gov/2006%20IEEE1588%20Agenda/Stein_Sub-nanosecond%2 01588%20final.pdf 2) I was thinking of locking a PLL to the Ethernet carrier in order to minimize the jitter between modules. Is there a continuous clock or encoded signal between frames? If there is nothing specified between frames do you think one can send some kind of clock or may that provoke some perturbations on a standard PHY? Thanks for you attention Pablo ------------------------- Pablo ALVAREZ SANCHEZ CERN - AB Department CH-1211 Geneva 23 GSM : +41 (0)76 48 72191 Phone : +41 (0)22 76 78431 Fax : +41 (0)22 76 69318 Building : 864-1-A30 _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.