); SAEximRunCond expanded to false Errors-To: [EMAIL PROTECTED] RETRY > Looking at the IEEE 1588 while implementing in your own FPGA seems > like an odd choice. It is an option, but you could fairly easy cook > up something which fits your needs. It is not too hard actually.
The main reason that Timing Solutions did its FPGA was to try to get down to sub-nanosecond level. That's very hard to do without hardware assist. And much of the available hardware assist is only good to approximately pci clock or a 25MHz clock, which was far too inaccurate to push the limits. The Timing Solutions experiments were designed to specifically push the limits of the technology as far as possible, to be NIC neutral and to discover the problems in developing the technology. All of this information should be in the Sam Stein, et al, paper, but I was only able to find the slides he talked from at http://ieee1588.nist.gov/2006%20IEEE1588%20Agenda/Stein_Sub-nanosecond%201588%20final.pdf His results showed ~98% of the measurements were in the +-2.5ns timing bin with a sigma of 0.9ns. This was on a cross-over cable, and when a hub was introduced the timing numbers became worse (a nearly uniform distribution over +/- 20ns). Most users of IEEE1588 don't need this level of performance, and can get by with cheaper solutions. Most people don't need a Cs standard either, but some small segment does. Warner _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.