From: Peter Vince <[EMAIL PROTECTED]> Subject: Re: [time-nuts] Of rubidium life and piggy-bank anemia.... Date: Sun, 02 Dec 2007 19:26:46 +0000 Message-ID: <[EMAIL PROTECTED]>
> > On Sun Dec 2 17:59 , Magnus Danielson <[EMAIL PROTECTED]> sent: > > >The problem is that he calls the DFFs latches. The problem with the term > >latches is that they sound like a good generic term, but really isn't. > > At the risk of showing my ignorance, could I ask you to explain the difference > please? A latch is a device in which the enable input allows data to flow freely through the latch, much as a buffer, when the enable input is active. As the enable goes inactive, it retains the last input level (or what it perceived as the last input level considering metastability). A D flip-flop updates its output on the rising (or falling) edge of the clock input. > > In message [EMAIL PROTECTED]>, Bruce Griffiths writes: > > > > The latches do NOT span clock domains, they are in the same domain > > as the counter. > > Sorry again, could you briefly explain what is meant by "clock domains"? A clock domain is a group of logic and DFFs clocked by a common clock source. Within the clock-domain all logic transitions occur synchronously to the clock of the clock domain. For modern ASIC and FPGA designs this allows for a much simplified analysis when combined with the ban of latches, since all logic signals, gate delays and routing delays can be statically analyzed and this allows for powerfull automatic placement and routing mechanisms. The respecting the setup time prior to the clock edge avoids metastability, and the term slack refers to the margin to the setup time. Between clock domains we assume asynchronous aspects, meaning that we risc metastability cause upset of values. By having an asynchronous signal being clocked into the clock domain using two DFFs clocked with the clock domain clock, the metastability issue becomes virtually removed. When designing ASICs and FPGAs you specifically divide the design into clock domains and sometimes one chooses to clock signals into a higher clocks in order to avoid many different clock domains. For FPGAs you have a limited amount of clock networks, but for very small clock domains you can handle it through a local clock domain setup, but it is a bit trickier to handle. Cheers, Magnus _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.