Bruce, > I've used plenty of CPLDs but see no reason to use one when it isnt > necessary.
The sentence in my perspective sounds a bit like this: I've used plenty of TTL and CMOS but see no reason to use them when I could fit them all on a CPLD. I do understand that some may not want to get into this kind of devices, however I see not much of a difference of learning you way with microcontrollers, CPLDs or with any digital IC's these days. CPLDs in general do bring simplicity but do require learning how to use them and for various reasons that may be undesirable and be confused with a complexity issue while it is just a learning issue. Very good, I do respect the usage of a bunch of CMOS/TTL chips if someone doesn't want to spend the effort of learning how to use a CPLD. When it comes to use CPUs for tasks better done by straight logic (and there are many examples out there) then I think it is not the right option. All understood so let's not discuss that any further. --- > No analog filtering of the D flipflop output is required. Now you got me lost. We were talking about a GPSDO, that is locking an VCXO on the GPS time (1pps or else) So by the end of it you need an analog signal to control the voltage input of the VCXO. Right ? Where you get that from ? If not by filtering your flip-flop output what else you have in between the 1pps and the VCXO ? CPU's DAC's ???? if so how does your complexity arguments still apply ? Luis Cupido _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.