Bruce Griffiths wrote: >> Dividing by 3 and then multiplying by 2 is not necessary, it just adds >> complexity and noise. >> >> Just use a pair of JK flipflops (no external gates required to divide by >> 3 unlike when using D flipflops) configured to divide by 3 and extract >> the 10MHz component in the divider output. >> For one version of a JK fliflop divide by 3 circuit see: >> http://www.play-hookey.com/digital/frequency_dividers.html >> >> >> > This divider is actually a poor design if the 2 fliflops both have Q=0 > (eg at startup or as the result of a transient) they stay in that state > forever (until powered down). > I should have checked for this, I'll find a better circuit that doesnt > have this undesirable behaviour. > > Bruce > > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > > Please ignore this comment the fixed logical one on the first flipflop J ensures that such a condition doesn't occur.
Flipflop state sequence A B 0 0 1 0 1 1 0 0 .... if A = 0, B=1 (on startup) than this state is left within 1 clock cycle: A B 0 1 1 0 1 1 0 0 ....... Bruce _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
