Stanley Reynolds wrote: > Thanks Pete not sure my wife will let another big box in the door. I was > thinking of some thing like this : > > http://www.onsemi.com/PowerSolutions/product.do?id=MC100E137FN > > a ECL 8-Bit Ripple Counter. And a 1Ghz oscillator make the measurement of > differences. This should get me to the 1ns level ? > > But looking at the sampling heads may be close to what I want, I will look > for some manuals on the web. I would want to transfer the data to a PC, would > I need a GPIB Interface and some software ? I'm trying to eliminate the extra > stuff like the scope tube and it's power supply and end up with a small box > to interface to the computer. > > > > Stanley, > > You can achieve subnanosecond timing resolution much more easily using a pair of ADC's sampling a quadrature pair of 10MHz sinewaves on the PPS leading edge using a Linear technology LTC1407A-1 dual simultaneous sampling ADC (available from LTC on a demo PCB complete with FPGA all you need is store and process the data). With care a resolution significantly better than 100ps is possible. This only has a 100ns range which should be more than sufficient for use with a timing receiver like an M12M or M12+T. Logic to count cycles can easily be added. The simplest and most reliable method being to synchronise a version of the PPS signal to both 10MHz zero crossings and use these synchronised outputs to sample a synchronous counter clocked by the 10MHz signal. One of the counter samples will be reliable and the other suspect due to metastability issues. The associated ADC samples can be used to work (calculate the 10MHz phase angle at the unsynchronised PPS leading edge and hence decide which synchroniser output meets the synchroniser flipflop setup and hold time constraints) out which of the 2 count samples is reliable.
Another technique is to use a triggered ramp as to interpolate the time to the next 10MHz zero crossing. This is very easy to do particularly when a modern capacitive charge redistribution ADC is employed - its input capacitance just becomes part of the ramp generator circuit. Resolution of 200ps or better is readily achieved without needing to use any expensive ECL parts. Either method is far cheaper and has higher resolution than sampling a counter clocked at 1GHz clock. A synchroniser clocked at 1GHz is essential for reliable operation when sampling the count of a 1GHz counter. Using a ripple counter is a particularly bad idea, guaranteeing reliable sampling is likely to be difficult to impossible unless the counter is capable of reliable operation at several GHz. The problem being the ripple clock propagation delay from one flipflop to the next. For this counter the input clock to output transition delay is typically over 4nsec whilst the clock to Q0 delay is about 1.7ns a difference of 2.3 cycles at 1 GHz. Bruce _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.