> -----Original Message----- > From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On > Behalf Of Bruce Griffiths > Sent: Wednesday, February 17, 2010 2:10 PM > To: Discussion of precise time and frequency measurement > Subject: Re: [time-nuts] DMTD to MMTD > > The latest version actually records time stamps from a continuously > running counter clocked at some at a constant frequency (100Mhz??)for > all channels simultaneously. > They may use a flag bit for each for each channel to indicate to which > channel or channels the zero crossing time stamp belongs.
Simpler than that.. it grabs 20 bit numbers and shoves them out in ASCII over a com port with an indication of which channel it was for. The FPGA has a 20 bit free running counter at 100 MHz. When an input changes state, it latches the counter, and shoves it out along with the channel number. They use an offset frequency >100 Hz so that you don't have to disambiguate the counter rollovers. (20 bits rolls over every 10+milliseconds counting at 100 MHz) I don't know if there's a FIFO in front of the UART (e.g. what if you get simultaneous zero crossings).. but I would expect there is. The "hard work" is in the zero crossing detector ahead of the FPGA. (and perhaps in the latching of the ZCD inputs into the FPGA). Given how long ago it was made, that FPGA isn't a huge one. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
