> >
> > I don't know if there's a FIFO in front of the UART (e.g. what if you get 
> > simultaneous zero
> crossings).. but I would expect there is.
> >
> > The "hard work" is in the zero crossing detector ahead of the FPGA. (and 
> > perhaps in the latching of
> the ZCD inputs into the FPGA).
> >
> > Given how long ago it was made, that FPGA isn't a huge one.
> >
> >
> Using 8 flag bits (one per channel) together with the associated time
> stamp is a little more efficient and very easy to do and it doesn't
> require a FIFO to ensure that simultaneous zero crossings aren't missed.
> 

Still need the FIFO..
Say you got one zero crossing at 0x01000 and the next at 0x01001  (where the 
number is the 20 bits in hex).. you'd still be sending the characters out the 
UART for the 0x01000 crossing when the next crossing occurred 10ns later.

If I were doing it today (and I have no idea how Steve built it 10 years ago), 
I'd do something like a character for channel number and direction (ascii 0 
through 7 for positive going, 8 through F for negative going) and 5 characters 
for the count (in hex), followed by a carriage return. All printable 
characters, easy for testing, no hiccups with DOS or some device driver trying 
to interpret binary, etc.

You've got 8 channels, each zerocrossing at about 200-300 Hz (the difference 
frequency is 123 or 124 Hz, so you get twice that many zero crossings), or 
about 1600-2400 messages/second.  At 6 characters per message, that's about 
10,000 characters per second, so you'd need a fairly fast UART to keep up. 
(OTOH, the article mentions dropping characters..)

They might have only used one direction of zero crossing, which gets you down 
to the 5000 characters per second, which you might be able to squeeze into a 
38.4kbps serial stream, especially if you go to a denser packing.  But you'll 
still need a FIFO.

Next time I see one of the FTL guys, I'll ask.

Jim

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