I'm certainly not the expert but can't you place a divide by 7 counter in the feedback loop of a phase lock loop. There is a fast version of the 4046 PPL chip that does 100Mhz and a divide by 7 is easy to rig with TTL.
On Tue, Dec 21, 2010 at 8:35 AM, Stephen Farthing <squir...@gmail.com> wrote: > > I want to multiply the output from my Efratom 101 (10Mhz) to clock a DDS at > 70 Mhz. Has anyone tried this? -- ===== Chris Albertson Redondo Beach, California _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
