On 05/02/11 15:20, jimlux wrote:
I agree, but if you want the clock rate to be changeable/selectable, driven arbitrarily by logic in the FPGA, you're kind of stuck.
There is always corner-cases. I quite intently left room for that as well. The general recommendation is still to avoid it unless you can show that there isn't a problem.
A typical scenario (which could be fixed by minimal external circuitry) is turning the clock entirely off to save power in the DAC/ADC. Or where you want to run the converters at a lower rate to save power when processing a narrower band signal.
A single gate outside would solve these problems. Let the FPGA hold state, and let minimal external HW handle the timing critical stuff. For some applications you need to compromise, but if you don't need to compromise there is no engineering challenge to be handled.
In the software radio area, we usually have at least two clocks in the system.. a CPU clock running at something like 66 or 75MHz (or something convenient) and a reference oscillator (used for generating the local oscillators, etc., as well as the sampling clocks) at 50-100 MHz, although the sampling might be divided down some from that. The CPU clock is generally of lower quality (e.g. not a TCXO, not necessarily good phase noise) and the reference oscillator is usually fairly good (TCXO or OCXO, good phase noise since it's being multiplied up to microwave frequencies, etc.) A low parts count approach to meeting the overall need might be to have a very small "clock FPGA" that is clocked ONLY by the external clock and generates the needed DAC and ADC clocks, with whatever dividing, etc. At least then, you don't have to deal with isolation from the CPU bus clock.
That is one solution.
That would be an alternative to adding a lot of external clock mux logic, with dividers and such. You might even be able to use a suitable onetime programmable FPGA in a small package to implement a "generic clock source" with enough sophistication, but still with minimal degradation.
For several designs you seem to be able to feed the clock separately from the clock source to the ADC/DAC and the FPGA and get the length matching work out. As soon as the data goes up on the chip it can be reclocked to whatever suitable for further processing.
Cheers, Magnus _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
