Gracias, Javier.
As you read in my previous email I'm basically
worried about close-in spurs (those that
will pass through the PLL loop filter).
will digest that 4th section... tks.
...
Since I'm inside an FPGA... I'm eager to get
spurs down without leaving the digital world...
Anyone knows any literature covering that ?
Thanks.
Luis cupido.
ct1dmk.
On 6/20/2011 4:52 PM, Javier Herrero wrote:
To reduce the spurii due to quantization distortion. Here is an
explanation, in Section 4
http://www.analog.com/static/imported-files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf
Regards,
Javier
El 20/06/2011 17:39, Luis Cupido escribió:
Well, if we really need to filter it out
we better filter the MSB and square it
again...
Why having a DAC for ???
Right ?
Luis Cupido.
ct1dmk.
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