@Tom
Unfortunately there are no free ADC channels in the concept
and there is a fixed adjustment (calibration) software routine
which I cannot change. Complete FPGA software is calculated
for a 100MHz clock. There is no possibility to change that.
So I dont have to fix a frequency- but a jittering problem.
But thank you anyway for the good idea.
Maybe I can use it in a later hardware & software version. I will
discuss this with the programmer of the FPGA.
@Bob
The TCXO I'm using is a AXTAL AXLE20-12 which comes with -135dBc/10kHz.
Unfortunately I havent any closer noise data. The TCXO has a electronic
frequency control input which works from 0.3 to 3V giving it a fdelta of
+-5ppm.
The initial freq. tolerance is +-2ppm and aging is +-1ppm/year.
As you suggested I also thought of giving it a narrow lowpass filter cause
the
only thing I need is a very low jitter on the edges of the 100MHz HCMOS
signal.
As we are using an intitial calibration routine (thats the one I cannot
change easily) and an additional working-calibration routine, a very slow
shifting in phase
isnt a problem as the w-calibration can be done quickly everytime before a
measurement (a sampling) will be taken. So the w-calibration will overwrite
the initial
calibration which datas have been copied at boottime to RAM before
programming the FPGA for operation.
Regards
Peter, DG4EK
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