Hi I suspect you can find a part with significantly better noise floor. "Very good" is around -170 dbc / Hz at a 10 KHz offset. There's a lot of room between that and -135.
Best guess is that you start rolling up at 1 KHz on a part like that. More or less you would get: 100 Hz -125 dbc / Hz 10 Hz -105 1 Hz -85 At the phase detector, you would have -85 - 20 log(100/10) = -95 dbc / Hz. At 10 Hz you would have -125. In both cases the TBolt is lower noise than the divided TCXO. A PLL with a 3db loop bandwidth of around 20 Hz should work just fine. Parts values on a loop like that should be very rational. The resulting combination of TCXO + TBolt would be more quiet than the TBolt alone. For that matter, your 10 KHz noise works out to -155 at 10MHz. You could lock anywhere inside 10 KHz and likely the TBolt + TCXO would still be more quiet than the TCXO alone. The problem there would be the noise floor of the divider and detector …. Bob On Sep 19, 2011, at 6:19 PM, Peter Krengel wrote: > @Tom > Unfortunately there are no free ADC channels in the concept > and there is a fixed adjustment (calibration) software routine > which I cannot change. Complete FPGA software is calculated > for a 100MHz clock. There is no possibility to change that. > So I dont have to fix a frequency- but a jittering problem. > But thank you anyway for the good idea. > Maybe I can use it in a later hardware & software version. I will > discuss this with the programmer of the FPGA. > > @Bob > The TCXO I'm using is a AXTAL AXLE20-12 which comes with -135dBc/10kHz. > Unfortunately I havent any closer noise data. The TCXO has a electronic > frequency control input which works from 0.3 to 3V giving it a fdelta of > +-5ppm. > The initial freq. tolerance is +-2ppm and aging is +-1ppm/year. > As you suggested I also thought of giving it a narrow lowpass filter cause the > only thing I need is a very low jitter on the edges of the 100MHz HCMOS > signal. > As we are using an intitial calibration routine (thats the one I cannot > change easily) and an additional working-calibration routine, a very slow > shifting in phase > isnt a problem as the w-calibration can be done quickly everytime before a > measurement (a sampling) will be taken. So the w-calibration will overwrite > the initial > calibration which datas have been copied at boottime to RAM before > programming the FPGA for operation. > > Regards > Peter, DG4EK > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
