I have not studied CPLDs but Actel has the only true Flash based FPGAs. The
flash cells directly control the FPGA fabric. As such, they are mostly immune
to Single Event Upset that plagues just about any other FPGA technology, and
there is no configuration step at power up.
Didier KO4BB
Sent from my BlackBerry Wireless thingy while I do other things...
-----Original Message-----
From: Azelio Boriani <azelio.bori...@screen.it>
Sender: time-nuts-boun...@febo.com
Date: Sat, 28 Apr 2012 00:57:42
To: Discussion of precise time and frequency measurement<time-nuts@febo.com>
Reply-To: Discussion of precise time and frequency measurement
<time-nuts@febo.com>
Subject: Re: [time-nuts] PICTIC II ready-made?
FPGA with internal flash memory to boot from, yes, but I think that small
CPLD haven't to boot anything: they should have the interconnection array
associated with the EEPROM cell array.
On Fri, Apr 27, 2012 at 11:52 PM, David <davidwh...@gmail.com> wrote:
> On Fri, 27 Apr 2012 22:13:55 +0200, Azelio Boriani
> <azelio.bori...@screen.it> wrote:
>
> >By "preload" I think you mean the configuration step of the logic. It
> seems
> >that the Xilinx one stops the clock after the configuration is done.
> Anyway
> >using small EEPROM based CPLDs you have no clock at all: there is no
> >configuration to load.
>
> Wouldn't that also apply to an EEPROM based FPGA? I have been
> thinking that SRAM based devices may be a better match in cases where
> you only want to have to program one device.
>
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