On Tue, 5 Jun 2012 08:03:53 -0700 Peter Monta <pmo...@gmail.com> wrote:
> o far I have a prototype board outputting bits from which GPS signals > on L1 and L2 have been successfully acquired and tracked. Next steps > are to play with acquiring some GPS L5, Glonass, and Galileo signals, > and to apply some minor cleanups to the hardware for the next spin. > > The current design files, including schematic, PCB layout and artwork, > HDL, support software, and a sample sky recording of simultaneous > wideband L1 and L2, are available here: > > http://pmonta.com/blog/2012/06/04/gnss-firehose/ > http://github.com/pmonta/GNSS_Firehose Very cool! I like it! And i imediatly buy one as soon as you produce some :-) I had a cursory look at the schematics and i would propose the following changes: * Connect all free pins of the FPGA to a 2.54mm header pin connector This would make extensions to the system a lot simpler. Up to the point of using a simple uC board for a full fledged GPSDO system. Additonally put onto this connecter an unused output of the LMK03806 and some power supply pins. * The XC6SLX9 is <10USD more expensive than the SLX6. I think the added value of having twice as much "real estate" would justify the additional price. * Connect the enable pin of the OSC1 to a 2-pin header, so it can be disabled with a simple jumper. And put a SMA connector into the path between OSC1 and the LMK03806 (probably not mounted by default) in order to make using an external clock source easier. I assume that you are running the ADCs in multiplexed mode and the FPGA at 128MHz clock? How about design tools for the FPGA? As far as i can tell, the ISE WebPack does not support the Spartan 6 family. Attila Kinali -- Why does it take years to find the answers to the questions one should have asked long ago? _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.