> Hi John, > > Congratulations on a good design. Thanks!
> Why the 78 MHz sample frequency ? Long story: it's mostly arbitrary, but at least with some ADCs, it's beneficial to spur performance if the first few dozen harmonics of the ADC clock rate and the most commonly-used test frequencies don't approach each other too closely. In this case I wanted to ensure good SFDR when measuring 5 and 10 MHz signals, so I went with a clock frequency that has no harmonics within 100 kHz of any harmonics of 5 MHz until 3.2 GHz. At that point, the 640th harmonic of 5 MHz is 50 kHz away from the 41st harmonic of 78.050 MHz. The resulting 50 kHz spur is somewhat dependent on input levels, but it's rarely worse than -130 dBc, well below the 5330A's spec limit of -100 dBc. Being in a predictable location far from the carrier, it could be removed in software, although I don't currently do that. There is a patent by Symmetricom (US 7,227,346) that discusses the problem in more detail. Their approach in the TSC 5120A was to use a pair of ADCs with inputs in quadrature at each phase detector, for a total of eight. This technique doesn't seem to be needed with the LTC2216s I used. They're well-behaved even near input frequencies deliberately chosen to cause trouble, like 7.805 MHz. -- john _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.