On the Bruce page there is a table with increasing stage amplification
from low-level to the output.
If this is the optimum for low jitter how does it connect to the
well-known rf design philosophy to have the highest amplification at the
first stage, not the last stage, to have maximum S/N ?
Any idea?
- Henry
Chris Hoffman, KG6O schrieb:
Thank you, Bruce!!! That is exactly the information I was looking for. I
sincerely appreciate the help.
-CH
On Jul 19, 2012, at 12:47, Bruce Griffiths <bruce.griffi...@xtra.co.nz> wrote:
The problem of optimal zero crossing detector design was essentially solved by
Oliver Collins in the 1990's.
Essentially a series of cascaded limiter stages with appropriate gain and
bandwidth distribution are used.
With a 10MHz 1V rms signal only 2-3 stages suffices.
However unless you need fs jitter less complex zero crossing detectors should
suffice.
1) a comparator (or line receiver) based design should achieve sub 10ps jitter.
2) AC coupling to the input of a CMOS (AC04, AHC04 LVC04) should achieve a
jitter of 1ps or less
3) A simple differential pair with AC coupled emitters (reduces asymmetry due
to component tolerances ) is capable of sub ps jitter.
There is a spreadsheet to assist design of Collins style zero crossing
detectors at:
http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html
<http://www.ko4bb.com/%7Ebruce/ZeroCrossingDetectors.html>
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