My 2.5nS TIC? Very simple: a 400MHz counter start-stop gated with the two signal to compare. I have published here the VHDL code for it few months ago. Really nothing new but simple and useful for a 35-40nS GPSDO PPS output from an OCXO. The Rb PPS wondering is actually under evaluation against the Z3815A.
On Sat, Sep 15, 2012 at 12:08 AM, Hal Murray <hmur...@megapathdsl.net>wrote: > > d...@montana.com said: > > Michael: Actually implementing a 16 bit DAC to its 1-bit minimum > resolution > > will be headache enough. You will gain a real education in good grounding > > practice, shielding, power supply stability and noise, and other Murphy > > intrusion. A 32 bit DAC IMHO, is impossible, and that's the name of that > > tune. > > The trick for this application is that you don't need full accuracy over > the > full range of the DAC. All you need is roughly linear and stable around > the > operating point. The PLL will take care of any offset. Any gain error is > just a minor change to the overall gain. > > This thread started with "16 bit PWM DAC". I think that matches the > requirements. > > I would expect a problem area would be filtering the PWM output. Anything > you don't filter out will turn into close in spikes. It might be fun to > try > to measure them. > > 64K/72 MHz is about 1 ms. 32bits at 72 MHz is 60 seconds. > > Has anybody compared DDS style DACs with PWM? The idea is to spread the > pulses out to make the filtering easier. Instead of 1111100000, you would > get to work with 1010101010 > > > -- > These are my opinions. I hate spam. > > > > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.