Hi Bob, Agreed.
I was looking around for some different ideas on frequency multiplication and stumbled across these "built in VCO" parts such as the CY2302. My first thought was that they seem to be targeted to multiplying and synchronizing clocks in digital systems rather than RF multiplication. Ultimate use of the DDS generated signal is as a high stability RF source for a very low power transmitter for use with amateur radio QRSS modes. The signals are typically frequency shift keyed or about 5 Hz and use slow data keying to permit long integration at the reception location. Transmitted Power levels are frequently 100 mW plus or minus, sometimes much lower. Frequency stability is needed. The data keying is usually time synced as well, commonly having a 10 minute frame rate, sometimes longer, sometimes much longer. The more I think of it, the more it seems that the better choice is the multiplier chain to get from 10 MHz to where I need to be. Perhaps I will have a go at building an 80 MHz VCXO and phase locking that to my external 10 MHz ref. There is another interesting chip, the SI-570, one version of which has a Vcontrol input for FM'ing. Locking this device to an external 10 MHz reference should not be much different than building a GPSDO. As I have discovered, with respect to these DDS chips, the signal out can never any better quality than the refclock going in - GIGO. Cheers, Graham ve3gtc -----Original Message----- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of Bob Camp Sent: August-30-13 1:21 PM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] frequency multiplication Hi A discrete VCXO and PLL chip will always outperform the "buit in VCO" silicon parts. The CY2302 is quite noisy even by silicon standards. Your doubler / tripler will give you good close in noise, but poor performance broadband. A lot depends on what the ultimate use for the DDS output is. The DDS it's self likely has enough issues noise and spur wise to make the quality of the clock driving it somewhat less important. Bob On Aug 30, 2013, at 12:56 PM, "Collins, Graham" <coll...@navcanada.ca> wrote: > > > Good day all, > > Lately I have been contemplating a variety of methods to take a high > stability 10 MHz reference multiply it up to a suitable frequency for use a > the reference clock for a DDS, for example 10 MHz to 80 MHz or 120 MHz (or > whatever). > > On method is to use simple diode based doublers and triplers to get to where > I want to be, that 10 x 2 x 2 x 2 = 80 or 10 x 3 x 2 x 2 = 120 or whatever > combinations that would accomplish the same thing. > > Another is the use of something like the Cypress CY2302 frequency multiplier > and zero delay buffer which uses a PLL to perform it's magic (i.e 2 or 4 or 8 > or 16 times multiplication). > > My goal is to be able to use the DDS to generate a stable frequency close to > the stability of the 10 MHz reference with good phase noise although the > latter criteria is ill defined and of lesser importance than frequency > stability at the moment. > > Anyone have any firsthand experience with the likes of the CY2302 and can > comment on their suitability for this task? > > Cheers, Graham ve3gtc > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
