dho...@gmail.com said: > The 32F4 (like lots of similar ARMs) uses a PLL to generate the internal > clocks from much lower frequency clock or crystal. Has anyone quantified > the stability of the synthesised clock?
I'm not familiar with the 32F4, but most of the SOC type ARM chips have ways to generate clocks by dividing the main clock and a way to feed those clocks out a pin. So collecting data would be a small amount of code to set things up and then your normal clock analysis setup. There would be additional noise depending upon the package (and board layout) and how much is going on in the chip, mostly how often other output pins are changing, especially the nearby ones. -- These are my opinions. I hate spam. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.