On 15/10/2014 10:29, Bruce Griffiths wrote:
The use of a synchroniser loses no information apart from fine details about the metastability response of the sampling flipflop. With a 10Hz offset and a 10MHz clock the sampling resolution is 100fs with the phase difference between the flipflop clock and data input transitions changing monotonically by 100fs between successive active clock transitions. Phase noise/jitter between the flipflop and data input transitions will typically result in a burst of state transitions at the synchroniser output rather than a single transition when the active clock transition and a data transition coincide..
Right, this is my understanding of what the white rabbit articles refers to as glitching and is why I know I have something wrong when I see no noise at all.
What I'm less sure about is what I should expect to see as the clock/data phase steps through the unstable region of the sampling flip flop's response. Whilst the synchroniser will ensure I get an output of some sort at each cycle, its going to take many cycles @100fs to step through before the sampling flip flop is stable again. Is this likely to appear as (random?) state transitions at the synchroniser output ? perhaps this region just gets lost in the mush of clock jitter ?
Typically a 74HC164 shift register has internal cycle to cycle sampling jitter of about 4ps or so when used as a mixer, a 74AC device has about 1/4 of this jitter or around 1ps. Faster CMOS devices have even less internal jitter.
It's on my to do list, but I don't have the parts to hand, yet. I'd like to see how far the flip flop approach goes and then I'll be able to compare and contrast with using a shift register.
Cheers Simon _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
