Verrry nice Stu, thank you, having both units obviously does have its  
advantages after all:-)
 
Pin 3 certainly controls the standby indication on the Z3811A and it's  
comforting to know it is indeed a solid ground during normal  operation.
 
However, given the low logic level seen on pin 2 I'm back to  thinking it 
might be preferable to fit a pull down resistor  to pin 2 when enabling stand 
alone mode rather than a direct  short.
 
A couple of quick measurements shows 0.223V across a 470ohm pull  down and 
0.446V across 1Kohm, the supposed indicated precision no doubt a  fluke:-) 
but at least indicating a consistent current to ground of approx  0.5mA.
 
So without knowing what's driving pin 2 I'm going back to a 470ohm pull  
down just to be on the safe side.
 
Regards
 
Nigel
GM8PZR
 
 
In a message dated 04/11/2014 09:38:25 GMT Standard Time,  
stewart.c...@gmail.com writes:

A wiring  diagram of the Z3809A cable interconnect cable was published
earlier on  this list.  That information appears to be incorrect.  The
cable  is actually wired pin 1 to pin 15, pin 2 to pin 14, etc.
Another way to  describe it is that for each wire in the cable, the pin
numbers on each end  of the cable add up to 16.

A mated pair of these units is running in my  lab with a scratch-built
interconnect cable following the above  rules.  This scratch-built
cable allowed access to the interconnect  signals while the system was
operating happily.  No lights were lit  except the green ON light on
the Ref-0 unit (Z3812A, no GPS) and the yellow  STBY light on the Ref-1
unit (Z3911A with GPS receiver).  The  following signals were observed
on the interconnect (pin numbers given for  the J5 interconnect socket
on the Ref-1 unit):

Pin 1:  9600  baud serial data (described below)

Pin 2:  logic low  (0.11V)

Pin 3:  Ground (0.00V)  Presence detect? (see  below)

Pin 4:  logic high (4.79V)

Pin 5:  inverted  Motorola PPS, high (5V) for 800ms, low for 200ms

Pin 6: "17 / 23 dBm"  signal from Ref-0 unit (see below)

Pin 7:  logic high  (4.48V)

Pin 8:  Ground (0.00V)

Pin 9:  logic low  (0.11V)

Pin 10: "17 / 23 dBm" signal from Ref-1 unit (see  below)

Pin 11:  inverted PPS, low 400us, high (5V)  otherwise

Pin 12:  logic low (0.12V)

Pin 13:  Ground  (0.00V)

Pin 14:  logic low (0.08V)

Pin 15:  logic high  (4.78V)

Pins 3, 8, and 13 appear to be firmly connected to  Ground.  (Note that
these are the three pins which are clipped short  on the HP
interconnect cable.)  On an unpowered, disconnected box  (either Ref-0
or Ref-1), pins 8 and 13 are connected to Ground (low  resistance) and
pin 3 is high impedance.  Presumably pin 3 on each box  (connected to
the grounded pin 13 on the other box) is used to sense the  presence of
the other box and/or the interconnect cable.

The timing  of the PPS signal on pin 11 matches precisely the timing of
the PPS signal  available on pins 1 and 6 of J6 (RS422/PPS) on the
active Ref-0 unit.   Presumably this signal is coming across the cable
from the Ref-0  unit.

Note: when the system is coming up from a cold start, SatStat on  the
unit with the GPS receiver (Ref-1) will show "[Ext 1PPS valid]" in  the
space where it shows "[GPS 1PPS valid]" after the survey is  complete.
It appears that the Ref-1 unit timing system is locking its  oscillator
to the PPS coming from the Ref-0 unit during this  time.

The timing of the PPS signal on pin 5 matches the timing of the  PPS
output described in the Motorola OnCore manual.  Presumably  this
signal is sourced by the Ref-1 unit to allow the Ref-0 unit to lock  to
GPS.  The edges of this PPS signal look very dirty compared to  the
signal on pin 11.  This may be an artifact of the homemade cable  used
for this experiment.  The HP cable clearly has an overall  shield
(visible through the cable sheath) and may have internal coax  or
twisted pair for these PPS signals.

When pin 5 and pin 11 are  observed together, the usual GPS sawtooth
pattern is  evident.

Someone discovered earlier that the both units will blink  their green
ON lights if the front-panel switch on either unit is set to 23  dBm
vice the normal 17.  Obviously each unit can communicate its  switch
status to the other unit.  They use pins 6 and 10 to do  that.  Pin 10
(on the Ref-1 unit) is high (~5V)  if the switch on  the Ref-1 unit is
in the 17 dBm position, and low in the 23 dBm position.  Pin 6 (on the
Ref-1 unit) gives the same indications for the switch on the  Ref-0
unit.

The serial data on pin 1 is transmitted at 9600 baud,  with a burst of
data every second.  The signal idles at logic low  (near 0V) and rises
to logic high (near 5V) during the burst.  This  may be the standard
for TTL (not RS-232) transmission of serial data, or it  may be
inverted.  The first few characters of one burst were  hand-decoded
from a scope trace as 0x40, 0x40, 0x45, 0x61, 0x0B, or ASCII  "@@Ea".
This appears to be the Motorola Oncore binary data format,  although
"Ea" does not appear to be a valid Motorola command or  response.
Perhaps the hand-decoding was in error.

One can use  SatStat, talking to the Ref-0 (non-GPS) box, to issue
queries and commands  to the GPS receiver.  The results are
inconsistent, but it seems that  at least some of the queries get
through and trigger responses.  If  the Ref-0 box is actually talking
to the GPS receiver, it must be doing so  through the interconnect
cable.  The specific wire in the cable used  for this (if any) has not
yet been identified.

An earlier post  speculated that the computer in each unit only had two
UARTs.  This  does not seem possible.  Clearly each unit uses one UART
to  communicate with the J8 diagnostic port.  The Ref-1 unit needs
another  UART to communicate with the GPS receiver. And both units need
to be able  to transmit the legacy Lucent timecode message out the J6
(RS422/1PPS)  port.  Perhaps there is a transmit-only UART coded into
the FPGA, or  perhaps one of the UARTs is timeshared with the Lucent
message, or perhaps  there is another UART chip hidden somewhere on the
board.

It seems  unlikely that the two units are sending serial data to each
other.   (No such data was observed on the interconnect.)  Instead,
they appear  to communicate their state to each other by means of logic
levels on  various pins of the cable.  The logic functions of pins 6
and 10 have  already been identified.  Further research is  needed.

Cheers!
--Stu
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