The CLK1 input circuit produces an output incompatiblr with the 3.3V CMOS deice it drives.A pair of pnp transistors in an otherwise similar circuit is capable of producing a 3.3V CMOS compatible output signal. Using independent voltage dividers to bias the transistor bases is a bad idea in that resistor tolerances may lead to a dc input offset of seeeveral tens of millivolts even with 1% resistors, Bruce
On Thursday, 25 December 2014 6:13 AM, Li Ang <lll...@gmail.com> wrote: http://www.qsl.net/bi7lnq/freqcnt_bi7lnq_v4.pdf this is my current board. I'm not a hardware guy, feel free to correct my mistakes. :) http://assets.fluke.com/manuals/6690____smeng0000.pdf schematic of cnt90 aka pm6690 Happy holidays Li Ang _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.